This work studies four carrier phase synchronizers (CPS) or carrier Phase Lock Loop (CPLL). The
synchronizers are based in a loop with VCO (Voltage Controlled Oscillator) that synchronizes the output feedback with the input. We consider four carrier synchronizers namely
the analog, hybrid, combinational and sequential. The difference between them is in the phase comparator. The main objective is to study the synchronizers output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio).University of Beira Interiorinfo:eu-repo/semantics/publishedVersio

Carvalho, José Pacheco de

Gameiro, Atilio

Reis, António

Rocha, José Ferreira da

English

UBibliorum repositorio digital da ubi

   Abstract— This work studies  four carrier phase synchronizers (CPS) or carrier Phase Lock Loop (CPLL). The synchronizers are based in a loop with VCO (Voltage Controlled Oscillator) that synchronizes the output feedback with the input. We consider four carrier synchronizers namely the analog, hybrid, combinational and sequential. The difference between them is in the phase comparator. The main objective is to study the synchronizers output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio). Index Terms—Synchronism, Digital Communications  I. INTRODUCTION The carrier phase synchronizer (CPS) is a Phase Lock Loop (PLL) with a particular phase comparator prepared to synchronize with input carrier signals [1, 2, 3, 4, 5, 6, 7, 8]. The PLL synchronizes its VCO directly with an input carrier signal [9, 10, 11, 12, 13, 14, 15, 16]. The PLL is a feedback device based in a phase comparator, a filter and a local oscillator VCO. The main input and VCO feedback enter the phase comparator. The phase error forces the VCO to follow the input carrier. So, the receiver VCO input is the band base signal that firstly modulated the transmitted emitter VCO carrier. This work studies four carrier phase synchronizers namely the analog, hybrid, combinational and sequential. The difference between them is only in the phase comparator since the other blocks are equals. Fig.1 shows the general blocks diagram of the carrier phase synchronizers.   Fig.1 Configuration of the carrier phase synchronizer  Kf is the phase comparator gain, F(s) is the loop filter, Ko is the VCO gain and Ka is the loop amplification that controls the root locus and hence, the loop desired characteristics. In prior and actual art-state was developed various synchronizers, now is necessary to know their performance. The motivation of this work is to create new synchronizers and to evaluate their performance. Following, we present the four carrier PLLs, namely the analog, the hybrid, the combinational and the sequential. After, we present the project and tests. Then, we present the results. Finally, we present the conclusions.   Manuscript received August 18, 2017; Supports from UBI and FCT. A. D. Reis is with the University of Beira Interior Covilha and Group of A. P. and Telecommunications, Portugal (e-mail: adreis@ ubi.pt). J. F. Rocha is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: frocha@ ua.pt). A. S. Gameiro is with the University of Aveiro and Institute of Telecommunications, Portugal (e-mail: amg@ ua.pt). J. P. Carvalho is with the University of Beira Interior Covilha and Group of A. P. and Telecom., Portugal (e-mail: pacheco@ ubi.pt).  II. FOUR CARRIER PLLs We present the four carrier PLLs, namely the analog, the hybrid, the combinational and the sequential. The difference between them is in the phase comparator [2].  A. Analog carrier PLL (PLL-ana)  The phase comparator of this carrier PLL is based on the ideal multiplier (analog component) (Fig.2).    Fig.2   Fig.2 Analog carrier PLL (PLL-ana)  The phase comparator inputs (main input and VCO output feedback) are both analog. Following Fig.3 shows the operation mode of the analog carrier PLL.    Fig.3 Waveforms of the analog carrier PLL (PLL-ana)  The output wave CLKs synchronizes in quadrature (90º) with the input wave CKEs. In phase (0º) the error signal E=1, in phase opposition (180º) E=-1 and in quadrature (90º) E=0. If the VCO frequency fVCO diminishes, tends to stay in phase (A>B) then fVCO increases and goes to the equilibrium point.  B. Hybrid  carrier PLL  (PLL-hib)  The phase comparator of this carrier PLL is based on the switch or real multiplier (hybrid component) (Fig.4).    Fig.4 Hybrid carrier PLL (PLL-hib)  The phase comparator main input is now digital, but the input coming from the VCO output feedback is still analog.  Carrier Phase Synchronizers Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro and Jose P. Carvalho Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 Following Fig.5 shows the operation mode of the hybrid carrier PLL.    Fig.5 Waveforms of the hybrid carrier PLL (PLL-hib)  The output wave CLKs synchronizes in quadrature (90º) with the input wave CKE. In phase, the error signal E=1, in phase opposition E=-1 and in quadrature E=0. If the VCO frequency fVCO diminishes, tends to stay in phase (A>B) then fVCO increases and goes to the equilibrium point.  C. Combinational carrier PLL (PLL-cmb)  The phase comparator of this carrier PLL is based on the exor gate (combinational component) (Fig.6).    Fig.6 Combinational carrier PLL (PLL-cmb)  The phase comparator inputs (main input and VCO output feedback) are both digital. The output is only function of the inputs.  Following Fig.7 shows the operation mode of the combinational carrier PLL.    Fig.7 Waveforms of the combinational carrier PLL (PLL-cmb)  The output wave CLK synchronizes in quadrature (90º) with the input wave CKE. In phase, the error signal E=1, in phase opposition E=0 and in quadrature E=0.5. If the VCO frequency fVCO diminishes, tends to stay in phase (A>B) then fVCO increases and goes to the equilibrium point.  D. Sequential carrier PLL (PLL-seq)  The phase comparator of this carrier PLL is based on the flip flop (sequential component) (Fig.8).     Fig.8 Sequential carrier PLL (PLL-seq)  The phase comparator inputs (main input and VCO output feedback) are both digital. The output is function of the inputs and phase comparator state (circuit with memory). Following Fig.9 shows the operation mode of the sequential carrier PLL.    Fig.9 Waveforms of the sequential carrier PLL (PLL-seq)  The output wave CLK synchronizes in phase opposition (180º) with the input wave CKE. In phase (0+), the error signal E=1, in phase (0-) E=0 and in phase opposition (180º) E=0.5. If the VCO frequency fVCO diminishes, tends to stay in phase (A>B) then fVCO increases and goes to the equilibrium point.  III. PROJECT, TESTS AND RESULTS We present the project, the tests and the results of the referred  synchronizers [5].  A. Project  We project all the synchronizers with the same loop gain conditions to have guaranteed results. The loop gain is Kl = Ka.Kf.Ko, where Kf and Ko are fixed. Ka is the variable parameter that controls the roots and loop characteristics. To facilitate the analysis, we use normalized values for the bit rate tx= 1baud, clock frequency fCK=1Hz, extern noise bandwidth Bn=5Hz and loop noise bandwidth Bl=0.02Hz. We apply a power signal Ps= A2ef with power noise Pn= No.Bn= 2σn2.∆τ.Bn, where σn is the noise standard deviation and ∆τ =1/fSamp is the sampling period. Then, the SNR is related with the noise variance σn2 SNR= Ps/Pn= A2ef/(No.Bn)= 0.52/(2σn2*10-3*5)= 25/σn2 (1) Now, for each synchronizer, we must measure the output jitter UIRMS versus input SNR.    - 1st order loop: The loop filter F(s)=1 has cutoff 0.5Hz, which is 25 times greater than Bl= 0.02Hz, it eliminates the high frequency but maintains the loop characteristics. The transfer function is  H(s)=G(s)1 G(s)+=+=+KdKoF ss KdKoF sKdKos KdKo( )( )                   (2) the loop noise bandwidth is Bl = KdKoKaKfKo4 4=  = 0.02Hz                                   (3)  Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018 So, with (Km=1, A=1/2, B=1/2, Ko=2π) and loop bandwidth Bl=0.02, we obtain respectively the Ka, for analog, hybrid, combinational and sequential synchronizers, then  Bl=(Ka.Kf.Ko)/4 = (Ka.Km.A.B.Ko)/4 -> Kaa=0.08*2/π      (4) Bl=(Ka.Kf.Ko)/4 = (Ka.Km.A.B.Ko)/4 -> Kah=0.08*2.2/π   (5) Bl=(Ka.Kf.Ko)/4 = (Ka*1/π*2π)/4 -> Kac=0.04              (6) Bl=(Ka.Kf.Ko)/4 = (Ka*1/2π*2π)/4 -> Kas=0.08              (7)  For the analog PLL, the jitter formula is   σφ2=Bl.No/Aef2=0.02*10-3*2σn2/0.52=16*10-5.σn2         (8) For the others PLLs, the jitter formula is more complicated.  - 2nd order loop:  It is not used here, but provides similar results.  B. Tests  We used the following setup to test the various  synchronizers (Fig.10).    Fig.10 Block diagram of the test setup  The receiver recovered clock with jitter is compared with the emitter original clock without jitter, the difference is the jitter of the received clock.  C. Jitter measurer (Meter)  The jitter measurer (Meter) consists of a RS flip flop, which compares the receiver clock random phase (CKR) with the emitter clock fixed phase (CKE). This relative random phase variation is the recovered clock jitter (Fig.11).    Fig.11 The jitter measurer (Meter)  The other blocks (reset integrator and sampler) convert this random phase variation into a random amplitude variation, which is the jitter histogram. Fig.12 illustrates the operation of the jitter measurer.     Fig.12 Waveforms at the jitter measurer  Then, the jitter histogram is sampled and processed by an appropriate program, providing the RMS jitter and the peak to peak jitter.  D. Results  We present the results in terms of  output jitter UIRMS  versus input SNR. Fig.13 shows the jitter-SNR curves of the four carrier PLLs: analog carrier PLL (PLL-ana), hybrid carrier PLL (PLL-hib), combinational carrier PLL (PLL-cmb), sequential carrier PLL (PLL-seq).  Fig.13 Jitter-SNR curves of  the four PLLs  (P-a, P-h, P-c, P-s)  We observe that, generally, the output jitter decreases almost exponentially with the input SNR increasing. We verify that, for high SNR, the carrier PLL without input limiter (PLL-ana) is disadvantageous over the others with input limiter (PLL-hib, PLL-cmb, PLL-seq). However, for low SNR, the carrier PLL with intern memory in its phase comparator (PLL-seq) is slightly disadvantageous over the others without intern memory in its phase comparator (PLL-ana, PLL-hib, PLL-cmb). This disadvantage can be minimized with a prefilter.  IV. CONCLUSIONS We studied four carrier PLLs, namely the analog (PLL-ana), the hybrid (PLL-hib), the combinational (PLL.cmb) and the sequential (PLL-seq).  We observed that, in general, the output jitter diminishes almost exponentially with the input SNR increasing. We verified that, for high SNR, the carrier PLL without input limiter (PLL-ana) is disadvantageous over the others with input limiter (PLL-hib, PLL-cmb, PLL-seq). This is comprehensible since the digital limiter noise margin ignores low noise spikes. However, for low SNR, the carrier PLL with intern memory in its phase comparator (PLL-seq) becomes disadvantageous over the others without intern memory in its phase comparator (PLL-ana, PLL-hib, PLL-cmb). This is comprehensible since the high noise spikes provokes random commutations causing the error state that contributes to the jitter. Anyway, this disadvantage can be minimized with a prefilter. These jitter-SNR observations can be useful, to choose the appropriate carrier PLL in each situation. In the future, we are planning to extend this study to other synchronizers types.  ACKNOWLEDGMENTS  The authors are grateful to the program FCT (Foundation for sCience and Technology).  REFERENCES [1] Jean C. Imbeaux, “performance of the delay-line multiplier circuit for clock and carrier synchronization”, IEEE Jou. on Selected Areas in Communications p.82 Jan. 1983.   Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018[2] Werner Rosenkranz, “Phase Locked Loops with limiter phase detectors in the presence of noise”, IEEE Trans. on Communications com-30 Nº10 pp.2297-2304. Oct 1982. [3] Hans H. Witte, “A Simple Clock Extraction Circuit Using a Self Sustaining Monostable Multivibrat. Output Signal”, Electronics Letters, Vol.19, Is.21, pp.897-898, Oct 1983. [4] Charles R. Hogge, “A Self Correcting Clock Recovery Circuit”, IEEE Tran. Electron Devices p.2704 Dec 1985. [5] Antonio D. Reis, Jose F. Rocha, Atilio S. Gameiro, Jose P. Carvalho “A New Technique to Measure the Jitter”, Proc. III Conf. Telecommunications pp.64-67 FFoz-PT 23-24 Apr 2001. [6] Marvin K. Simon, William C. Lindsey, “Tracking Performance of Symbol Synchronizers for Manchester Coded Data”, IEEE Transactions on Communications Vol. com-2.5 Nº4, pp.393- 408, April 1977. [7] J. Carruthers, D. Falconer, H. Sandler, L. Strawczynski, “Bit Synchronization in the Presence of Co-Channel Interference”, Proc. Conf. on Electrical and Computer Engineering pp.4.1.1- 4.1.7, Ottawa-CA 3-6 Sep. 1990. [8] Johannes Huber, W. Liu “Data-Aided Synchronization of Coherent CPM-Receivers” IEEE Transactions on Communications Vol.40 Nº1, pp.178-189, Jan. 1992. [9] Antonio D’Amico, A. D’Andrea, Reggianni, “Efficient Non- Data-Aided Carrier and Clock Recovery for Satellite DVB at Very Low SNR”, IEEE Jou. on Sattelite Areas in Comm. Vol.19 Nº12 pp.2320-2330, Dec. 2001. [10] Rostislav Dobkin, Ran Ginosar, Christos P. Sotiriou “Data Synchronization Issues in GALS SoCs”, Proc. 10th International Symposium on Asynchronous Circuits and Systems, pp.CD-Ed., Crete-Greece 19-23 Apr. 2004. [11] N. Noels, H. Steendam, M. Moeneclaey, “Effectiveness Study of Code-Aided and Non-Code-Aided ML-Based Feedback Phase Synchronizers”, Proc. IEEE Int Conf. on Comm.(ICC’06) pp.2946-2951, Ist.-TK, 11-15 Jun 2006. [12] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “Carrier Phase Lock Loop and Bit Phase Lock Loop”, Proc. IX Symposium on Enabling Optical Network and Sensors (SEONs) p.CD-Edited, Aveiro-PT 1-1 July 2011. 12] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “The Electromagnetic Wave and the Principle of the Telecommunications”, Proc. VI Symposium on Enabling Optical Network and Sensors (SEONs 2008) p.87, Porto-PT 20-20 June 2008. [13] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “Carrier Phase Lock Loop and Bit Phase Lock Loop”, Proc. IX Symposium on Enabling Optical Network and Sensors (SEONs) p.CD-Edited, Aveiro-PT 1-1 July 2011. [14] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho “Optical Digital Communication Systems and Synchronism”, Proc. 7th UBI International Conference on Engeneering (for Economic Development) - ICEUBI 2013, pp. CT8-11.7, Covilhã-PT 27-29 November 2013. [15] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Synchronizers Operating Synchronously and Asynchronously by All Transitions at Rate”, Proc. SEONs 2016 - XIII Symposium on Enabling Optic Network and Sensors, PP. 31- 34, Covilha, 8 July 2016. [16] A. D. Reis, J. F. Rocha, A. S. Gameiro, J. P. Carvalho, “Asynchronous Sequential Symbol Synchronizers based on Pulse Comparison by Positive Transitions at Quarter Bit Rate”, Proc. World Congress on Engineering 2016, ‘WCE 2016’, pp.257-261, London-UK, 29 June - 1 July 2016. Proceedings of the World Congress on Engineering 2018 Vol I WCE 2018, July 4-6, 2018, London, U.K.ISBN: 978-988-14047-9-4 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)WCE 2018

Carrier phase synchronizers

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Carrier phase synchronizers

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