17 research outputs found
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Measurement of the Positive Muon Anomalous Magnetic Moment to 0.46 ppm
We present the first results of the Fermilab Muon g-2 Experiment for the
positive muon magnetic anomaly . The anomaly is
determined from the precision measurements of two angular frequencies.
Intensity variation of high-energy positrons from muon decays directly encodes
the difference frequency between the spin-precession and cyclotron
frequencies for polarized muons in a magnetic storage ring. The storage ring
magnetic field is measured using nuclear magnetic resonance probes calibrated
in terms of the equivalent proton spin precession frequency
in a spherical water sample at 34.7C. The
ratio , together with known fundamental
constants, determines
(0.46\,ppm). The result is 3.3 standard deviations greater than the standard
model prediction and is in excellent agreement with the previous Brookhaven
National Laboratory (BNL) E821 measurement. After combination with previous
measurements of both and , the new experimental average of
(0.35\,ppm) increases the
tension between experiment and theory to 4.2 standard deviationsComment: 10 pages; 4 figure
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems
Effective reconfigurable design: The FASTER approach
While fine-grain, reconfigurable devices have been available for years, they are mostly used in a fixed functionality, "asic-replacement" manner. To exploit opportunities for flexible and adaptable run-time exploitation of fine grain reconfigurable resources (as implemented currently in dynamic, partial reconfiguration), better tool support is needed. The FASTER project aims to provide a methodology and a tool-chain that will enable designers to efficiently implement a reconfigurable system on a platform combining software and reconfigurable resources. Starting from a high-level application description and a target platform, our tools analyse the application, evaluate reconfiguration options, and implement the designer choices on underlying vendor tools. In addition, FASTER addresses micro-reconfiguration, verification, and the run-time management of system resources. We use industrial applications to demonstrate the effectiveness of the proposed framework and identify new opportunities for reconfigurable technologies. © 2014 Springer International Publishing Switzerland