Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

The genetic algorithm has been applied to the VLSI module placement problem. This algorithm is an iterative, evolutional approach. A placement configutation is represented by a set of primitive features such as location and orientation, and the features are arranged in the form of a two-dimensional bitmap chromosome. The representation is flexible, and can handle arbitrarily shaped cells, and pads, and is applicable to the placement of macro cells, and gate arrays. Three new versions of genetic operators, namely, crossover, inversion and mutation, are used to explore the solution space. Crossover creates new configurations by combining attributes from a pair of existing configurations. This feature passing scheme constitutes the primary difference between our genetic approach and the other traditional searching techniques. Inversion enables more uniform inheritance of features from one generation to the next, and mutation prevents the algorithm from getting trapped at local optima. We have pointed out that the bitmap representation enables the algorithm to divide the entire solution space into a set of feature-equivalent classes, or schemata where each class contains a set of solutions with common physical attributes. We show that the genetic algorithm adaptively biases the search based on the past observed fitness of the schemata. We also demonstrated the power of the genetic algorithm experimentally for macro cell placement, and obtained satisfactory results.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/29041/1/0000074.pd

Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits

Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI) computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks

Application of the genetic algorithm for computer-aided design of VLSI layout.

This research investigates the application of the Genetic Algorithm for four VLSI layout problems, Gate Matrix Layout, Partitioning, Standard Cell, and Macro Cell Placement. In permutation problems such as placement and gate matrix optimization, the traditional binary genetic operators cause conflicts, and hence cannot be applied without modifications. This research investigates various chromosomal representations and the genetic operators that eliminate such conflicts, and adapt the GA for efficient optimization of these CAD problems. The Standard Cell Placement algorithm uses three crossover operators, Order, PMX, and Cycle crossover, in order to manipulate the placement efficiently during the optimization process. The algorithm was tested against TimberWolf 3.3 on five industrial circuits consisting of 100 to 800 cells, and the performance was comparable. The Macro Cell Placement algorithm uses a bit matrix to represent various sizes, shapes and orientations of macro cells. For chromosomes having thousands of bits, the processing of a bit matrix during crossover is much faster than a linear bit string. The algorithm was used to place five MCNC benchmark circuits, and the complete layout including routing was obtained by interfacing the algorithm to the Berkeley CAD tools. The Gate Matrix algorithm uses a novel implementation of the GA in combination with beam search. The principles of beam search have been used in order to resolve the conflicts in the traditional GA, while simultaneously reducing the search space. The algorithm produces better results than simulated annealing and a graph theoretic approach on published netlists. The GA has been implemented for circuit partitioning with a significant improvement in result quality compared to the Fiduccia-Matthesis algorithm. It can optimize a cost function with multiple constraints. Separate algorithms have been developed for bipartitioning and multiway partitioning. The bipartitioning problem is represented as a binary chromosome. Efficient bit-mask operations perform crossover, mutation, and net cut evaluation 32 bits at a time, without unpacking. The multiway partitioning algorithm has a global view of the problem, and optimizes all the necessary partitions simultaneously. The algorithms were tested on the MCNC benchmark circuits, and the cut size obtained was lower than that for the conventional Fiduccia-Matthesis algorithm.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/104200/1/9501030.pdfDescription of 9501030.pdf : Restricted to UM users only

VLSI cell placement techniques

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macr