CLIQUES FOR IDENTIFICATION OF GENE SIGNATURES FOR COLORECTAL CANCER ACROSS POPULATION

poster abstractIntroduction: Colorectal cancer (CRC) is one of the most common cancers diagnosed worldwide. Studies have correlated CRC with dietary habits and environmental conditions. We developed a novel network based approach where cliques and their connectivity profiles explained the variation and similarity in CRC across four populations- China, Germany, Saudi Arabia and USA. Methods: Networks generated after data preprocessing were analyzed individually based on topological and biological features. Using greedy algorithm, cliques of various sizes were identified in each network and size 7 cliques were further analyzed based on their clique connectivity profile (CCP). Our algorithm considered the interaction of cliques based on two parameters: (i) Identification of common (links) genes; (ii) CliqueStrength. The cliques were evaluated by two conditions (a) Maximum number of common genes across cliques and highest CliqueStrength and (b) Minimum number of common genes across cliques and highest CliqueStrength. Results: Large numbers of genes are found to be common between USA, China and Germany. Highly scored nodes based on topological parameters are TP53, SRC, ESR1, SMAD3, GRB2, CREBBP, EGFR, SMAD2, and CSN2KA1. Signal transduction, protein phosphorylation etc., were found to be important GO biological processes. Number of unique size 7 cliques identified in all the population is 650. 49 common cliques identified included genes- EGFR, GRB2, PIK3R1, PTPN6, BRCA1, SMAD2, TP53, CSN2 etc. We found 20 cliques that are uniquely identified for USA, 10 for Germany and one for China. Cliques include genes that are both well studied, less-studied in CRC; but are targets in other cancers. Conclusion: With CCP, we were able to identify commonality, uniqueness and divergence among the populations. Furthermore, comparing all cliques (their CCP) as gene-signatures across populations can help to identify efficient drug targets. Results were consistent with other studies and demonstrate the power of cliques to study CRC across populations

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Process Design for the Production of Ethylene from Ethanol

This project considers using ethanol dehydration as a means to mass-produce ethylene. 2.3MM tonnes of a 95% ethanol / 5% water feed will be converted into 1MM tonnes of 99.96% pure ethylene per year using a series of adiabatic, fixed-bed catalytic reactors operating at 750°F and 600psi. The catalyst is gamma-alumina in the form of 1cm diameter spherical pellets. After the dehydration process, the product will be purified using two flash separation units, an adsorption unit with zeolite 13X sorbent, and finally a cryogenic distillation unit. The plant will be located in São Paulo, Brazil. Because ethanol production in Brazil is seasonal, the plant will operate only 280 days per year at a very high capacity. This includes 30 days worth of on-site feed storage. After conducting an analysis of the sensitivity of the plant’s Net Present Value and Internal Rate of Return to ethylene and ethanol prices, it was determined that while profitability is not attainable in the current market (which prices ethanol at $0.34/lb and ethylene at$0.60/lb), profitability is attainable should ethylene prices rise to $0.64/lb and ethanol prices fall to$0.305/lb

Fourth general elections in Andhra Pradesh

Call number: LD2668 .T4 1968 R36Master of Scienc

A New Control Strategy For Cascaded H-Bridge Multilevel PV Inverter With Distributed MPPT For Grid Connected Applications

A three - phase  modular  cascaded H-bridge multilevel inverter for a grid-connected photovoltaic (PV) system is presented in this project. To maximize the solar energy extraction of each PV string, an individual maximum power point tracking (MPPT) control scheme is applied, which allows the independent control of each dc-link voltage. PV mismatches may introduce unbalanced power supplied to the three-phase system. To solve this issue, a control scheme with modulation compensation is proposed. The three-phase modular cascaded multilevel inverter prototype has been built. A fuzzy controller is implemented in this project in the place of PI controller to balance the three phase grid current . Each H-bridge module is connected to a 185-W solar panel. Simulation results are presented to verify the feasibility of the proposed approach in MATLAB /SIMULINK environment.

A high sensitivity and low power circuit for the measurement of abnormal blood cell levels

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply

A VGA linearity improvement technique for ECG analog front-end in 65nm CMOS

This paper presents a 65nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5-100mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loopgain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25-50dB gain, and post-layout simulations showed a 15dB reduction in the harmonic distortion for 20mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108μm2 silicon area and consumes 0.43μA from a 1.2V power supply

A positive feedback-based op-amp gain enhancement technique for high precision applications

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage, and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gainboosting technique. The proposed opamp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1V supply. The circuit draws a total static current of 295μA and occupies 5000μm2 of silicon area

A novel current reference in 45nm cmos technology

In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/0C against temperature variation of -400C –1200C and line sensitivity of 337ppm/V against supply variation of 0.6–1.8V, while consuming 135uW from 1.8V supply and occupying 5184um

A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area