La futura orden europea de retención de cuentas para simplificar el cobro transfronterizo de deudas en materia civil y mercantil

Resumen: La futura Orden Europea de Retención de Cuentas nace para hacer frente a los problemas que comportan la diversidad de los derechos procesales civiles de los Estados miembros y el trato de las medidas cautelares en el Reglamento Bruselas I a la hora de asegurar la ejecución en el patrimonio del deudor en litigios trandfronterizos. Se tratará de una medida con carácter cautelar, con efectos in rem y adoptada sin audiencia previa al deudor. En la Propuesta de Reglamento, que regula el proceso de adopción y ejecución de la Orden, se remite a los respectivos derechos nacionales para cuestiones sobre las que no existe consenso en los distintos ordenamientos procesales. Este instrumento se tiene que poner en relación con la revisión de la regulación de las medidas cautelares en el Reglamento Bruselas I, que lo podrían hacer menos interesante en la práctica.   Palabras clave: retención de cuentas, medidas cautelares, revisión del Reglamento Bruselas I. Abstract: The future European Account Preservation Orden has been created in order to deal with the problems arising because of the diversity of the procedural laws of the Member States and the present regulation of provisional measures in the Brussels Regulation, which make the enforcement on the debtor’s assets in cross-border disputes difficult. The European Account Preservation Order is a provisional measure with effects in rem which is adopted without a prior hearing of the debtor. In the Regulation’s Proposal, which also deals with the procedure for the adoption and the enforcement of the Order, reference is made to the respective national laws for cuestions in which they strongly differ. This instrument must be considered in relation with the new regulation of provisional measures in the Revision of the Brussels I Regulation, which may render the present project less interesting.   Key words: account preservation, provisional measures, revision of the Brussels I Regulation

Transformación transfronteriza: exigencias para el estado miembro de acogida Comentario a la stjue c-378/10 (vale építési kft)

Resumen: En la sentencia sobre el asunto C-378/10 (VALE Építési Kft) el TJUE retoma lasafirmaciones realizadas en un obiter dictum de la sentencia Cartesio y afirma de nuevo el derecho delas sociedades constituidas conforme al derecho de un Estado miembro a trasladar su domicilio socialadoptando una forma societaria del Estado miembro de acogida con mantenimiento de su identidad. Lalimitación de la posibilidad de transformación a sociedades a sociedades constituidas según el derechodel Estado miembro de acogida resulta contraria a la libertad de establecimiento reconocida en los arts.49, 54 TFUE. A falta de una 14ª Directiva en materia de sociedades relativa a la transferencia de lasede social, el derecho del Estado miembro de acogida debe obedecer a los principios de equivalenciay efectividad. Palabras clave: libertad de establecimiento, traslado del domicilio social, transformación transfronteriza,principios de equivalencia y efectividad.Abstract: In the judgement on the case C-378/10 (VALE Építési Kft) the ECJ resumes its obiterdicta statement from the decision Cartesio and affirms the right of the companies governed by the lawof a Member State to transfer their registered office maintaining their legal personality. The limitation ofthe rules on conversion to companies of the host Member State is contrary to the freedom of establishmentgranted in Art. 49, 54 TFEU. In the absence of a 14th Company Law Directive on the cross-bordertransfer of the registered office the law of the host Member States must be in accordance with the principlesof equivalence and effectiveness.Key words: freedom of establishment, transfer of registered office, cross-border conversion,principles of equivalence and effectiveness

Task scheduling techniques for asymmetric multi-core systems

As performance and energy efficiency have become the main challenges for next-generation high-performance computing, asymmetric multi-core architectures can provide solutions to tackle these issues. Parallel programming models need to be able to suit the needs of such systems and keep on increasing the application’s portability and efficiency. This paper proposes two task scheduling approaches that target asymmetric systems. These dynamic scheduling policies reduce total execution time either by detecting the longest or the critical path of the dynamic task dependency graph of the application, or by finding the earliest executor of a task. They use dynamic scheduling and information discoverable during execution, fact that makes them implementable and functional without the need of off-line profiling. In our evaluation we compare these scheduling approaches with two existing state-of the art heterogeneous schedulers and we track their improvement over a FIFO baseline scheduler. We show that the heterogeneous schedulers improve the baseline by up to 1.45 in a real 8-core asymmetric system and up to 2.1 in a simulated 32-core asymmetric chip.This work has been supported by the Spanish Government (SEV2015-0493), by the Spanish Ministry of Science and Innovation (contract TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), by the RoMoL ERC Advanced Grant (GA 321253) and the European HiPEAC Network of Excellence. The Mont-Blanc project receives funding from the EU’s Seventh Framework Programme (FP7/2007-2013) under grant agreement no 610402 and from the EU’s H2020 Framework Programme (H2020/2014-2020) under grant agreement no 671697. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047. M. Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243).Peer ReviewedPostprint (author's final draft

POSTER: Exploiting asymmetric multi-core processors with flexible system sofware

Energy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while keeping high performance. However, it is not known yet whether such systems are ready to handle parallel applications. This paper fills this gap by evaluating emerging parallel applications on an asymmetric multi-core. We make use of the PARSEC benchmark suite and a processor that implements the ARM big.LITTLE architecture. We conclude that these applications are not mature enough to run on such systems, as they suffer from load imbalance. Furthermore, we explore the behaviour of dynamic scheduling solutions on either the Operating System (OS) or the runtime level. Comparing these approaches shows us that the most efficient scheduling takes place in the runtime level, influencing the future research towards such solutions.This work has been supported by the Spanish Government (SEV2015-0493), by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), by the RoMoL ERC Advanced Grant (GA 321253) and the European HiPEAC Network of Excellence. The Mont-Blanc project receives funding from the EU's Seventh Framework Programme (FP7/2007-2013) under grant agreement number 610402 and from the EU's H2020 Framework Programme (H2020/2014-2020) under grant agreement number 671697. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047. M. Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243).Peer ReviewedPostprint (author's final draft

On the maturity of parallel applications for asymmetric multi-core processors

Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how portable are the current HPC applications for such supercomputing systems. Specifically we evaluate several execution models on an ARM big.LITTLE AMC using the PARSEC benchmark suite that includes representative highly parallel applications. We compare schedulers at the user, OS and runtime levels, using both static and dynamic options and multiple configurations, and assess the impact of these options on the well-known problem of balancing the load across AMCs. Our results demonstrate that scheduling is more effective when it takes place in the runtime system level as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the European Union's Horizon 2020 research and innovation programme under grant agreement No 671697 and No. 779877. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104.Peer ReviewedPostprint (author's final draft

Impact of a training program on the surveillance of Clostridioiaes difficile infection

A high degree of vigilance and appropriate diagnostic methods are required to detect Clostridioides difficile infection (CDI). We studied the effectiveness of a multimodal training program for improving CDI surveillance and prevention. Between 2011 and 2016, this program was made available to healthcare staff of acute care hospitals in Catalonia. The program included an online course, two face-to-face workshops and dissemination of recommendations on prevention and diagnosis. Adherence to the recommendations was evaluated through surveys administered to the infection control teams at the 38 participating hospitals. The incidence of CDI increased from 2.20 cases/10 000 patient-days in 2011 to 3.41 in 2016 (P < 0.001). The number of hospitals that applied an optimal diagnostic algorithm rose from 32.0% to 71.1% (P = 0.002). Hospitals that applied an optimal diagnostic algorithm reported a higher overall incidence of CDI (3.62 vs. 1.92, P < 0.001), and hospitals that were more active in searching for cases reported higher rates of hospital-acquired CDI (1.76 vs. 0.84, P < 0.001). The results suggest that the application of a multimodal training strategy was associated with a significant rise in the reporting of CDI, as well as with an increase in the application of the optimal diagnostic algorithm

CATA: Criticality aware task acceleration for multicore processors

Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities by scheduling tasks to the most appropriate cores. However, these schedulers may suffer from priority inversion and static binding problems that limit their expected improvements. Based on the observation that task criticality information can be exploited to drive hardware reconfigurations, we propose a Criticality Aware Task Acceleration (CATA) mechanism that dynamically adapts the computational power of a task depending on its criticality. As a result, CATA achieves significant improvements over a baseline static scheduler, reaching average improvements up to 18.4% in execution time and 30.1% in Energy-Delay Product (EDP) on a simulated 32-core system. The cost of reconfiguring hardware by means of a software-only solution rises with the number of cores due to lock contention and reconfiguration overhead. Therefore, novel architectural support is proposed to eliminate these overheads on future manycore systems. This architectural support minimally extends hardware structures already present in current processors, which allows further improvements in performance with negligible overhead. As a consequence, average improvements of up to 20.4% in execution time and 34.0% in EDP are obtained, outperforming state-of-the-art acceleration proposals not aware of task criticality.This work has been supported by the Spanish Government (grant SEV2015-0493, SEV-2011-00067 of the Severo Ochoa Program), by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316, TIN2012-34557, TIN2013-46957-C2-2-P), by Generalitat de Catalunya (contracts 2014-SGR- 1051 and 2014-SGR-1272), by the RoMoL ERC Advanced Grant (GA 321253) and the European HiPEAC Network of Excellence. The Mont-Blanc project receives funding from the EU’s Seventh Framework Programme (FP7/2007-2013) under grant agreement no 610402 and from the EU’s H2020 Framework Programme (H2020/2014-2020) under grant agreement no 671697. M. Moret´o has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047. M. Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243). E. Castillo has been partially supported by the Spanish Ministry of Education, Culture and Sports under grant FPU2012/2254.Peer ReviewedPostprint (author's final draft