Energy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while keeping high performance. However, it is not known yet whether such systems are ready to handle parallel applications. This paper fills this gap by evaluating emerging parallel applications on an asymmetric multi-core. We make use of the PARSEC benchmark suite and a processor that implements the ARM big.LITTLE architecture. We conclude that these applications are not mature enough to run on such systems, as they suffer from load imbalance.
Furthermore, we explore the behaviour of dynamic scheduling solutions on either the Operating System (OS) or the runtime level. Comparing these approaches shows us that the most efficient scheduling takes place in the runtime level, influencing the future research towards such solutions.This work has been supported by the Spanish Government (SEV2015-0493), by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de
Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), by the RoMoL ERC Advanced Grant (GA 321253) and the
European HiPEAC Network of Excellence. The Mont-Blanc project receives funding from the EU's Seventh Framework Programme (FP7/2007-2013) under grant agreement number 610402 and from the EU's H2020 Framework Programme (H2020/2014-2020) under grant agreement number 671697.
M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047. M. Casas
is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie
Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243).Peer ReviewedPostprint (author's final draft

Ayguadé Parra, Eduard

Badia Sala, Rosa Maria

Casas Guix, Marc

Chronaki, Kallia

Labarta Mancho, Jesús José

Moreto Planas, Miquel

Rico, Alejandro

Valero Cortés, Mateo

English

Casas, Marc

UPCommons. Portal del coneixement obert de la UPC

POSTER: Exploiting Asymmetric Multi-Core Processorswith Flexible System SofwareKallia Chronaki∗‡, Miquel Moretó∗‡, Marc Casas∗, Alejandro Rico+,Rosa M. Badia∗†, Eduard Ayguadé∗‡,Jesus Labarta∗‡ and Mateo Valero∗∗Barcelona Supercomputing Center, Barcelona, Spain‡Universitat Politècnica de Catalunya - BarcelonaTech, Barcelona, Spain +ARM, Austin, Texas†Research Institute (IIIA) - Spanish National Research Council (CSIC), Barcelona, SpainABSTRACTEnergy efficiency has become the main challenge for highperformance computing (HPC). The use of mobile asym-metric multi-core architectures to build future multi-coresystems is an approach towards energy savings while keep-ing high performance. However, it is not known yet whethersuch systems are ready to handle parallel applications.This paper fills this gap by evaluating emerging parallelapplications on an asymmetric multi-core. We make useof the PARSEC benchmark suite and a processor that im-plements the ARM big.LITTLE architecture. We concludethat these applications are not mature enough to run onsuch systems, as they suffer from load imbalance.Furthermore, we explore the behaviour of dynamic schedul-ing solutions on either the Operating System (OS) or theruntime level. Comparing these approaches shows us thatthe most efficient scheduling takes place in the runtime level,influencing the future research towards such solutions.1 IntroductionEnergy efficiency has become the main challenge for futureparallel computing designs [14], motivating prolific researchto face the Power Wall. An interesting approach towardsenergy efficiency is the use of asymmetric multi-core archi-tectures [2, 17] with different types of cores targeting differ-ent performance and power optimization points. Such sys-tems have been successfully deployed in the mobile domain,where simple in-order cores (little) have been combined withaggressive out-of-order cores (big) to build these systems.Many researchers are pushing towards building future par-allel systems with asymmetric multi-cores [9, 10, 12, 13, 23]and even mobile chips [20]. However, it is unclear if currentparallel applications will benefit from these asymmetric plat-forms. Load balancing and scheduling are two of the mainchallenges in utilizing such heterogeneous platforms, as theprogrammer has to consider them from the very beginningto obtain an efficient parallelization.ACM ISBN 978-1-4503-2138-9.DOI: 10.1145/1235In this work we evaluate the suitability of modern asym-metric multi-core platforms for highly parallel applications.First, we demonstrate that out-of-the-box parallel applica-tions do not run efficiently on asymmetric multi-cores as theasymmetry of the system leads to load imbalance.When load-balancing techniques are not included in theoriginal application, we evaluate alternative solutions that,without relying on the programmer, can leverage the op-portunities that asymmetric systems offer. These solutionsconsist of dynamic schedulers on either the OS or on theruntime system level. We use a state of the art dynamic OSscheduler that is aware of the asymmetry of the platform.Another approach is the use of a runtime system that is re-sponsible to schedule the workload to the appropriate idlecores dynamically. This is done with the use of a moderntask-based programming model that allows the specificationof inter-task dependences and lets the runtime system totrack dependences between tasks. We compare and anal-yse the outcome of this evaluation in terms of performance,power and energy.Although there has been remarkable research on asym-metric systems, we consider that their experimental eval-uation is limited compared to our work. First, there aremany works that base their evaluation on a simulated oremulated environment [1, 2, 11–13, 15–17, 19, 21–23, 25, 26],in contrast to our real asymmetric system. Furthermore,many works use either random task dependency graph gen-erators or scientific kernels instead of real scientific applica-tions [5,7,22,24]. Finally, many of the existing works do notpresent power and energy results [5, 11,17,22,25,26].2 The ARM big.LITTLE ArchitectureThe ARM big.LITTLE [6,10] is a modern asymmetric multi-core architecture that has been successfully deployed in themobile market. In this work, we make use of one of the com-mercially available development boards featuring a big.LITTLEarchitecture: the Hardkernel Odroid-XU3 development board.The Odroid-XU3 includes an 8-core Samsung Exynos 5422chip with four ARM Cortex-A15 (big) cores and four Cortex-A7 (little) cores. For the remainder of the paper, we referto Cortex-A15 cores as big and to Cortex-A7 cores as little.Scheduling a set of processes on an asymmetric multi-core system is more challenging than the traditional pro-cess scheduling on symmetric multi-cores. An efficient OSscheduler has to take into account the different characteris-tics of the core types of the system. The ARM big.LITTLEsystems provide three mainstream OS schedulers: cluster10246810124 5 6 7 8Avg speedup00.511.522.533.544 5 6 7 8Avg power (Watts)00.20.40.60.811.21.41.61.824 5 6 7 8Avg normalized energy00.20.40.60.811.21.44 5 6 7 8Avg EDP0257Static threading GTS Task-basedFigure 1: Average results when running on 4 to 8 cores with 4 of them big. Speedup is over 1 little core,static threading on 4 little cores is the baseline of energy consumption and EDPswitching [6], in-kernel switch [18] and global task schedul-ing (GTS) [6]. GTS allows running applications on all coresin the asymmetric multi-core and is considered as the mostsophisticated scheduler. In GTS, all cores are available andvisible to the OS scheduler, and this scheduler is aware ofthe characteristics and each core type. GTS tracks the CPUutilization of each process and dynamically schedules highCPU utilization processes to big cores and low CPU utiliza-tion processes to little cores. As a result, cores are activeaccording to the characteristics of the running processes.3 EvaluationThe experiments of this work are performed on the Hard-kernel Odroid XU3 described in Section 2. In these experi-ments, we set the big cores to run at 1.6GHz and the littlecores at 800MHz through the cpufreq driver.We measure the performance, power and energy of theoriginal PARSEC codes [3] together with a task-based im-plementation of nine benchmarks1 of the suite [4]. For spacepurposes we only show the average results among these bench-marks. The original codes make use of the pthreads libraryfor all the selected benchmarks, while the task-based imple-mentation is done using the OmpSs programming model [8].The OmpSs applications follow the same parallelization strat-egy implemented with OpenMP 4.0 task annotations.In the search of the optimal solution, we compare threedifferent scenarios of parallel execution when transferringthe scheduling responsibility to different levels of the soft-ware stack: (a) Static Threading: the scheduling responsibil-ity is on the application level. (b) OS Scheduling (GTS): theOS is responsible for performing the scheduling. Specificallywe use the GTS provided by ARM described in Section 2.(c) Task-based: the runtime system is responsible for thedynamic scheduling.Figure 1 shows the average results among the evaluatedbenchmarks. We refer to the system configurations as B+Lwhere B is the number of big cores and L is the number oflittle cores. The speedup chart of Figure 1 shows that theStatic threading approach does not benefit from adding littlecores to the system. In fact, this approach brings an average15% slowdown when adding four little cores (configuration4+4). This is a result of the static thread scheduling; thesame amount of work is assigned to each core, so when thebig cores finish the execution of their part, they become idleand under-utilized. GTS achieves a limited speedup of 5%1The benchmarks used are: blackscholes, bodytrack, can-neal, dedup, facesim, ferret, fluidanimate, streamcluster andswaptions.with the addition of four little cores to the 4+0 configuration.The addition of a single little core brings a 22% slowdown(from 4+0 to 4+1) and requires three additional little cores toreach the performance of the symmetric configuration (con-figuration 4+3). Finally, the Task-based approach alwaysbenefits from the extra computational power as the run-time automatically deals with load imbalance. Performanceimprovements keep growing with the additional little cores,reaching an average improvement of 16% over the symmetricconfiguration when 4 extra cores are added.The power chart of Figure 1 shows oppositional benefitsamong the three approaches. We can see that Static thread-ing and GTS benefit from asymmetry, effectively reducingaverage power consumption. Static threading reduces powerconsumption when moving from the 4+0 to the 4+4 systemby 23% while GTS does so by 6.2%. On the other hand,the task-based approach keeps the big cores busy for most ofthe time so it maintains the average power nearly constant.By keeping the power stable, the energy consumption of thetask-based approach shown in the third chart of Figure 1 isminimized since it only depends on the execution time.To see the impact on both performance and energy effi-ciency we plot the average energy delay product (EDP) onthe rightmost chart of Figure 1. In this chart the lower val-ues are the better. We observe that the task-based approachis the one that has the best performance-energy combina-tion for the asymmetric configurations since it maintainsthe lowest EDP for all cases. Static threading manages toreduce the average EDP by 7% while GTS and task basedapproaches do so by 10% and 37% respectively.4 ConclusionsIn this paper we examine the maturity of asymmetric multi-core systems to support emerging parallel applications, show-ing results for performance, power, energy and EDP. Throughour comparison of the three scheduling approaches, we con-clude that the task-based approach is the optimal solutionto dynamically balance the load among the asymmetric re-sources. Contrarily to the static and OS scheduling ap-proaches, the task-based approach constantly improves per-formance as asymmetry is increasing. Moreover, relying onthe runtime system for the efficient scheduling keeps powerstatic which results in energy savings. Finally, according tothe EDP results, the conclusion is that the task-based ap-proach offers the optimal performance and energy trade-offfor asymmetric systems.25 References[1] A. Agarwal and P. Kumar. Economical DuplicationBased Task Scheduling for Heterogeneous andHomogeneous Computing Systems. In IACC, 2009.[2] S. Balakrishnan, R. Rajwar, M. Upton, and K. K. Lai.The impact of performance asymmetry in emergingmulticore architectures. In ISCA, pages 506–517, 2005.[3] C. Bienia. Benchmarking Modern Multiprocessors.PhD thesis, Princeton University, January 2011.[4] D. Chasapis, M. Casas, M. Moreto, R. Vidal,E. Ayguade, J. Labarta, and M. Valero. PARSECSs:Evaluating the Impact of Task Parallelism in thePARSEC Benchmark Suite. Trans. Archit. CodeOptim., 2015.[5] K. Chronaki, A. Rico, R. M. Badia, E. Ayguade´,J. Labarta, and M. Valero. Criticality-aware dynamictask scheduling for heterogeneous architectures. InICS, pages 329–338, 2015.[6] H. Chung, M. Kang, and H.-D. Cho. HeterogeneousMulti-Processing Solution of Exynos 5 Octa withARM big.LITTLE Technology. Technical report,Samsung Electronics Co., Ltd., 2013.[7] M. Daoud and N. Kharma. Efficient Compile-TimeTask Scheduling for Heterogeneous DistributedComputing Systems. In ICPADS, 2006.[8] A. Duran, E. Ayguade´, R. M. Badia, J. Labarta,L. Martinell, X. Martorell, and J. Planas. Ompss: aProposal for Programming Heterogeneous Multi-CoreArchitectures. Parallel Processing Letters, 21, 2011.[9] A. Fedorova, J. C. Saez, D. Shelepov, and M. Prieto.Maximizing Power Efficiency with AsymmetricMulticore Systems. Communications of the ACM,52(12), 2009.[10] P. Greenhalgh. big.LITTLE Processing with ARMCortex-A15 & Cortex-A7. ARM White Paper, 2011.[11] M. A. Iverson, F. O¨zgu¨ner, and G. J. Follen.Parallelizing Existing Applications in a DistributedHeterogeneous Environment. In HCW, 1995.[12] J. A. Joao, M. A. Suleman, O. Mutlu, and Y. N. Patt.Bottleneck identification and scheduling inmultithreaded applications. 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Topcuoglu, S. Hariri, and M.-Y. Wu.Performance-Effective and Low-Complexity TaskScheduling for Heterogeneous Computing. IEEETrans. Parallel Distrib. Syst., 13(3), 2002.[25] K. Van Craeynest, S. Akram, W. Heirman, A. Jaleel,and L. Eeckhout. Fairness-aware Scheduling onsingle-ISA Heterogeneous Multi-cores. In PACT, 2013.[26] K. Van Craeynest, A. Jaleel, L. Eeckhout, P. Narvaez,and J. Emer. Scheduling heterogeneous multi-coresthrough performance impact estimation (pie). InISCA, pages 213–224, 2012.AcknowledgmentsThis work has been supported by the Spanish Government(SEV2015-0493), by the Spanish Ministry of Science andInnovation (contracts TIN2015-65316-P), by Generalitat deCatalunya (contracts 2014-SGR-1051 and 2014-SGR-1272),by the RoMoL ERC Advanced Grant (GA 321253) and theEuropean HiPEAC Network of Excellence. The Mont-Blancproject receives funding from the EU’s Seventh FrameworkProgramme (FP7/2007-2013) under grant agreement num-ber 610402 and from the EU’s H2020 Framework Programme(H2020/2014-2020) under grant agreement number 671697.M. Moreto´ has been partially supported by the Ministryof Economy and Competitiveness under Juan de la Ciervapostdoctoral fellowship number JCI-2012-15047. M. Casasis supported by the Secretary for Universities and Researchof the Ministry of Economy and Knowledge of the Govern-ment of Catalonia and the Cofund programme of the MarieCurie Actions of the 7th R&D Framework Programme ofthe European Union (Contract 2013 BP B 00243).3

POSTER: Exploiting asymmetric multi-core processors with flexible system sofware

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POSTER: Exploiting asymmetric multi-core processors with flexible system sofware

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