A 64-channel inductively-powered neural recording sensor array

This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.Ministerio de Ciencia e Innovación TEC2009-0844

Implementing energy saving algorithms for Ethernet link aggregates with ONOS

During the last few years, there has been plenty of research for reducing energy consumption in telecommunication infrastructure. However, many of the proposals remain unim-plemented due to the lack of flexibility in legacy networks. In this paper we demonstrate how the software defined networking (SDN) capabilities of current networking equipment can be used to implement some of these energy saving algorithms. In particular, we developed an ONOS application to realize an energy-aware traffic scheduler to a bundle link made up of Energy Efficient Ethernet (EEE) links between two SDN switches. We show how our application is able to dynamically adapt to the traffic characteristics and save energy by concentrating the traffic on as few ports as possible. This way, unused ports remain in Low Power Idle (LPI) state most of the time, saving energy.Comment: 8 pages, 10 figure

A power efficient neural spike recording channel with data bandwidth reduction

This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

A low-power reconfigurable ADC for biomedical sensor interfaces

This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3μW from a 1V voltage supply.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications

This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog frontend and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.Ministerio de Economía y Empresa TEC2016-80923-

A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation

A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioral models simulations were carried out to prove the correct functionality of the proposed approach.Ministerio de Economía y Competitividad TEC2016-80923-

On the Credibility of a Target Zone: Evidence from the EMS

We provide some new evidence on the credibility of the Exchange Rate Mechanism of the European Monetary System. To that end, we use of several credibility indicators, analysing the complete EMS history. We also compare the prediction qualities of the different indicators, and apply them to the experience of the new ERM linking the currencies of non-euro area Member States to the euro.Exchange rates, European Monetary System.

I Concurso Latinoamericano de Investigación Teatral "César Rengifo" Fallo

I Concurso Latinoamericano de Investigación Teatral "César Rengifo" Fall

A self-calibration circuit for a neural spike recording channel

This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2 , with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Article Mindfulness Abilities Are Associated with Anxiety Levels, Emotional Intelligence, and Perceived Self-Efficacy

This study examined the relationship between anxiety, emotional intelligence, perceived self-efficacy, and mindfulness abilities. A total of 205 Spanish university students were assessed for mindfulness (Freiburg Mindfulness Inventory-14), state-trait anxiety (State-Trait Anxiety Inventory), emotional intelligence (Trait Meta-Mood Scale-24), and general perceived self-efficacy (General Self- Efficacy Scale). The Student’s t-test was used to evaluate the possible differences between sexes for the study variables. Multiple regression analyses were conducted for each sex independently to evaluate the relationship between mindfulness and the other psychological variables, using mindfulness dimensions as a dependent variable. The results showed significant differences between females and males in mindfulness dimensions of self-control (p < 0.001) and acceptance (p = 0.012), and state (p = 0.005) and trait anxiety (p < 0.001). Multiple linear regression analyses revealed that the models for the relationship between mindfulness dimensions (attention, self-control, acceptance, and self-perception) and the other variables differed between females and males. Our results suggest that anxiety, emotional intelligence, and general perceived self-efficacy may be related to mindfulness abilities among a sample of Spanish university students. These findings could inform the development of targeted intervention programs to improve these psycho-emotional abilities