This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. It also performs the adjustment of the Programmable Gain Amplifier (PGA) gain to maximize the input voltage range of the analog-to-digital conversion. The circuit, which consists on a frequency-controlled signal generator and a digital processor, operates in foreground, is completely autonomous and integrable in an estimated area of 0.026mm 2 , with a power consumption around 450nW. The calibration procedure takes less than 250ms to select the configuration whose performance is closest to the required one.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Delgado Restituto, Manuel

Rodríguez Pérez, Alberto

Rodríguez Vázquez, Ángel Benito

Ruiz Amaya, Jesús

Sawan, Mohamad

English

idUS. Depósito de Investigación Universidad de Sevilla

A Self-Calibration Circuit for a Neural Spike Recording ChannelAlberto Rodríguez-Pérez1, Jesús Ruiz-Amaya1, Manuel Delgado-Restituto1, Mohamad Sawan2 and Ángel Rodríguez-Vázquez11Institute of Microelectronics of Seville and University of Seville Tlf.: +34 954 466 667 Fax: +34 954 466 600{alberto, ruiz, mandel}@imse-cnm.csic.es2Polystim Neurotechnologies LaboratoryDept. of Electrical Engineering, École Polytechnique de Montréalmohamad.sawan@polymtl.caAbstract - This paper presents a self-calibration circuit for a neu-ral spike recording channel. The proposed design tunes thebandwidth of the signal acquisition Band-Pass Filter (BPF),which suffers from process variations corners. It also performsthe adjustment of the Programmable Gain Amplifier (PGA) gainto maximize the input voltage range of the analog-to-digital con-version. The circuit, which consists on a frequency-controlledsignal generator and a digital processor, operates in foreground,is completely autonomous and integrable in an estimated area of0.026mm2, with a power consumption around 450nW. The cali-bration procedure takes less than 250ms to select the configura-tion whose performance is closest to the required one. I. INTRODUCTIONImplantable neural sensors provide relevant informationfor neuroscientists to understand brain´s operation and arehence key tools for the prevention and treatment of neural dis-eases. The combination of these sensors with wireless tech-nologies has enabled the development of efficient BrainMachine Interfaces (BMI) for both animals and humans andhas paved the way for the treatment of neural diseases like ep-ilepsy and the like. These interfaces consist of MultiElectrodeArrays (MEAs) implanted in the cortex, together with low-power mixed-signal and RF circuits for signal digitalizationand wireless transmission [1-8].Because these interfaces deal with extremely weak signals,careful filtering and amplification are needed for correct oper-ation [9]. Actually, programmability of both the amplifiergain and the bandpass filter poles is required to achieve cor-rect adaptation of the front-end response to the input stimuli.The rationale for gain programmability is that the amplitudeof the signal depends on the position of the electrode with re-spect to the sensed neuron. Regarding filter programmability,it is needed to compensate for electrical process parametersdeviations  intrinsic to any IC implementation [10]. Differentworks have confronted these issues by incorporating program-mability at circuit level [4-8]. However, programming is madein most cases in open loop and, to the best of our knowledge,there is no integrated solution yet addressing self-calibrationfor this sort of interfaces.In this work we present a calibration mechanism for theneural sensor channel previously presented in [11]; this neuralchannel has proven in silicon through a 130nm CMOS chip not yet published. The system first calibrates the bandpass fil-ter to set its bandwidth at 200Hz-7kHz and then calibrates theProgrammable Gain Amplifier (PGA) gain to maximize thevoltage amplitude at the input of the Analogue-to-DigitalConverter (ADC). Both calibrations are completed as fore-ground process. The calibration circuitry is completely auton-omous and can be embedded together with the rest of theneural sensor interface circuitry within the available neuralchannel area defined by the electrode pitch. The combinationof these two components hence results into a self-calibratedneural recording channel.The calibration algorithm and the associated circuitry aredescribed in Section II. Section III shows the simulation re-sults to illustrate the performance of the proposed circuit. Sec-tion IV ends with the conclusions of the work. II. CALIBRATION OF THE CHANNELFig.1 shows the architecture of the proposed neural spikechannel. It consists of a Band-Pass Low-Noise Amplifier (BP-LNA), which conditions the signal from the electrode,followed by a PGA and an ADC [11].Since each channel is affected by different processvariations parameters and owing to the fact that the sensedneural signal levels depend on the position of the electrodeswith respect to the neurons, the calibration process has to becarried-out separately for each channel.The calibration process is split in three steps, according theflow diagram shown in Fig.2. First, the input of the system isconnected to a frequency-controlled signal generator tocalibrate the low-pass and high-pass frequencies of the BP-Band-limited LNALP ctrlHP ctrlSignalGeneratorNeuralSignalADCPGASpike detection and Feature ExtractionProgrammable Gain Amplifier ADCCalibrationCircuitryVthDinFig. 1: Neural sensor channel architecture978-1-4577-1470-2/11/$26.00 ©2011 IEEE 464LNA. After that, the input of the system is switched to theelectrode and the PGA is calibrated to maximize the dynamicrange of the ADC. Once the system is calibrated, it isconfigured to detect and transmit the information about thespikes positions and features. To that purpose an algorithm todetermine the neural spike threshold voltage is ran as abackground process similar to that in [12]. The BP-filter andPGA calibrations are explained in detail in the followingsubsections.A. BP-filter calibrationAs it has been stated, the BP-LNA bandwidth is subject tochanges due to process variations. To compensate for thesechanges, two bit-programmability is introduced to controlboth the position of the high-pass ( ) and low-pass( ) poles. The former controls the value of the pseu-do-resistor whereas the latter controls the value of the load ca-pacitance [11]. The objective of the calibration flow is to adjust these con-trol bits to set the BP-band from 200Hz to 7kHz. For that pur-pose, three main circuits are involved during the BP-filtercalibration procedure (see Fig. 1): 1) a frequency-controlledsignal generator, which provides input waveforms to theLNA; 2) a digital circuit, which controls the calibration flowand determines the bits-configurability; and 3) a PGA andADC to extend to full-range and monitor the output signalfrom the LNA. The PGA and the ADC were previously re-ported in [11]. Herein, the two first circuits will be detailed. A.1 Frequency-controlled signal generator.Fig. 3(a) shows the block diagram of the signal-generator.This circuit provides pseudo-sinusoidal waveforms with verylow amplitude (around 2mV) at the frequency of the inputclock signal ( ). It consists of: 1) a charge pump, whichgenerates a truncated triangular waveform at the input clockfrequency; 2) a band-pass filter, which attenuates by a factor4 and filters high-order harmonics of the output signal fromthe charge pump; and 3) an attenuator, which reduces the sig-nal amplitude to the required levels for the LNA and filtersthermal noise. Detailed schematics of these circuits are illus-trated in Fig. 3(b), (c) and (d), respectively. Three clock fre-quencies are used along the calibration procedure (obtainedfrom the division of the 800kHz system clock), which are195.3125Hz, 1.5625kHz and 6.25kHz. Depending on the se-lected frequency, the charge pump is reconfigured by meansof two control bits ( ) which modify the slope of the tri-angular waveform and guarantee that the high and low valuesare not reached more than a 15% of the period of the inputclock. This reduces the high order harmonics of the triangularwaveform signal. In the same way, the band-pass filter isreconfigured to set the low pass frequency such that the highorder harmonics are attenuated. The worst-case total powerconsumption of the frequency-controlled signal generator isaround 370nW and the estimated silicon area is 0.02mm2.A.2 Digital calibration circuit.The process flow of the BP-filter calibration is shown inFig.4. First, the signal generator is programmed to work at theband-pass frequency (1.5625kHz). Setting the BP-filter to thewidest band, the PGA is calibrated to maximize the input dy-namic range of the ADC. Once it is finished, the system storesthe maximum value of the output signal under this configura-BP – LNA calibrationFrequency-controlled signal generatorEnd Calibration?HP and LP frequenciesYesNoNeural Input signalPGAcalibrationEnd Calibration?PGAcontrol bitsYesNo Neural Spike DetectionNeural Input signalForeground CalibrationFig. 2: Global calibration processHPctrl<1:0>LPctrl<1:0>clkb1 b2–Charge Pumpclk outb1b2Vbp VbpVinVbpVoutx1x2x12C1Biasing Circuitrya)b)c)50nA÷4BPFC2 C31b 2b1b 2b1bCC4CCLb11b 1bVoutVinVCM1M12.5kVoutATTENUATOR÷140Vind)÷135ATTENUATORVoutC1bFig. 3: Frequency-controlled signal generator: (a) block diagram, (b) charge-pump, (c) BP-filter and (d) attenuator.fin = 1.56kHzSetLPctrl = “00”HPctrl = “11”SetLPctrl = “11”HPctrl = “11”CalibratePGA CalculateVreffin = 6.25kHzVmax >0.75*Vref?LPctrl - 1YesNoLP-filtercontrol bitsfin = 195HzSetHPctrl = “00”Vmax >0.75*Vref?HPctrl + 1YesNoHP-filter control bitsEnd BP-LNA calibrationFig. 4: BP-filter calibration flow465tion, that is, the reference amplitude.The next step is the calibration of the LP-frequency. Thesignal generator is configured to create a 6.25-kHz signal andthe controls bits of the LP-filter are configured to set the low-est frequency. The ADC is configured to sample the input sig-nal at 80kHz. The calibration is performed by comparing themaximum output value of the system for a 6.25kHz input withthe stored BP-band reference. If the drop of the first is equiv-alent or lower than 3dB (75%), the LP-frequency is correctedand the calibration ends. In other case, the LP-frequency is ris-en to the next step and the comparison is performed again.This routine is repeated until either the drop voltage is lowerthan 3dB with respect to the stored BP-band amplitude refer-ence or the LP-frequency is configured at its widest value.The same procedure is followed to complete the calibrationof the HP-frequency. First, the frequency controlled signalgenerator is configured to compose a 195.32Hz signal, thatwill be used as the input of the system. The HP-pole is set toits highest value at the beginning, and the ADC samples theinput signal at 20kHz, which is compared with the stored ref-erence value to determine if the calibration ends (if it is high-er), or continue with the next HP-pole position.It is worth mentioning that the proposed procedure couldbe successfully applied for an arbitrary number of calibrationbits as long as the drop voltage between the different configu-rations was higher than the resolution of the signal at the out-put LNA. In this design, the effective resolution (ENOB) ofthe LNA output signal is around 5 bits for an output swing of480mV. This implies that the minimum change of amplitudewhich could be distinguished would be: (1) B. PGA calibrationThe calibration of the PGA starts by switching the signalfrom the electrode directly to the input of the calibrated BP-LNA of the recording system. Then, the system follows a cal-ibration flow in which the gain of the PGA is adjusted using asuccessive approximation algorithm similar to that of the SARADCs, in which the 3-bits are successively set starting withthe most significant one and continuing with the rest until theleast significant. In this case, the system sets the MSB of the PGA gain con-trol bits to ‘1’, while the others remain to ‘0’. Then, the outputof the recording channel is analysed during a certain time inorder to detect if the signal is saturated (it exceeds the 95% ofthe full-scale) or not. In the first case, the MSB is switched to‘0’; otherwise, it is kept to ‘1’. The next iteration starts switch-ing the next bit to ‘1’ and, hereinafter, the same analysis is per-formed. The calibration ends repeating the explainedalgorithm for the third bit. III. SIMULATION RESULTSThe bandwidth of the LNA presented in [11] is tuned from200 Hz to 7 kHz by following the proposed calibration proce-dure. Before that, the LNA has been simulated on typical con-ditions in order to extract the bandwidth for the differentconfigurations. The results for the high-pass and low-pass fil-tering are shown in Fig.5 (a) and (b), respectively,According to these results, it can be easily inferred that theconfiguration  and should be selected by the calibration procedure, since it pro-vides the closest bandwidth to the required one. Fig. 6 shows the chronogram of the calibration procedure.It starts by waiting around 30ms until the circuits reach theirstationary response. After that, the ADC is enabled and thePGA calibration is carried out. A detailed view is shown inFig. 6(a), where the frequency-controlled signal generatorprovides a pseudo-sinusoidal wave at 1.5625kHz while theADC samples the LNA output at 20kS/s. Since the LNA out-put swing is around 500mVpp, a gain equal to 2( ) is selected to not exceed the 95% of thefull-scale range. Once the PGA gain has been set, the calibra-tion procedure stores the maximum amplitude of the ADCoutput. Next, it begins the calibration of the low frequencypole. At this point, the signal generator is reconfigured to pro-vide an input tone at 6.25kHz and the ADC sampling rate isincreased to 80kS/s. As shown in Fig. 6(b), the procedurestarts using the configuration bits with lower bandwidth( ) and looks for the setting whose attenua-tion is closer to the required one (75%). Finally, the procedureis repeated for the high frequency pole, with the signal gener-ator providing a 195.3125Hz input tone and the ADC sam- Output swing2ENOB 1–------------------------------- 480mV25 1–----------------- 15.5mV= =HPctrl<1:0> 01= LPctrl<1:0> 11=102 10300.050.10.150.20.25 Ref. amplitude=0.236mVfi(Hz)             Logarithmic scaleMax. amplitude(V)  3dB-loss --> 0.167mVPole=443HzPole=221HzPole=52HzPole=23HzHPctrl<1:0>=00HPctrl<1:0>=01HPctrl<1:0>=10HPctrl<1:0>=112 4 6 8 10 12 14 16 18 2000.050.10.150.20.25 Ref. amplitude=0.236mVfi(kHz)Max. amplitude(V)  3dB-loss --> 0.164mVPole=11.976kHzPole=9.792kHzPole=7.936kHzPole=6.618kHzLPctrl<1:0>=00LPctrl<1:0>=01LPctrl<1:0>=10LPctrl<1:0>=11(a)(b)Fig. 5: LNA amplitude attenuation versus the input frequency for the different configurations in the: (a) high-pass and (b) low-pass filtering.PGA<2:0>=001LPctrl<1:0> 11=466pling at 20kS/s. A detailed view is shown in Fig. 6(c). As itcan be checked, the selected configuration is the required one( , ).A similar procedure has been carried out in several techno-logical and environmental corners. In all cases, the control bitshas been successfully selected. IV. CONCLUSIONSA calibration procedure to tune the bandwidth of a LNAand the gain of a PGA for a neural spike recording channelhave been presented. The procedure only requires a frequen-cy-controlled signal generator and digital circuitry to performthe calibration, while the rest of the needed blocks (ADC andbiasing), are reused from the recording channel. The proposedcalibration is performed as a foreground process and takes lessthan 250ms.The estimated area and power consumption of the dedicat-ed blocks are around 0.026mm2 and 450nW, respectively.The procedure has successfully selected the configurationclosest to the required specifications in all considered corners.ACKNOWLEDGMENTSThis work has been supported by the Spanish Ministry ofScience & Innovation under grant TEC2009-08447, the Juntade Andalucía under grant TIC-02818 and the 2007-2013FEDER Programme.REFERENCES[1] R. R. Harrison et al., “A Low-Power Integrated Circuit for aWireless 100-Electrode Neural Recording System,” IEEE J.Solid-State Circ., vol. 42(1), pp. 123-133, Jan. 2007.[2] M.S. Chae et al., “A 128-Channel 6mW Wireless Neural Re-cording IC With Spike Feature Extraction and UWB Transmit-ter,” IEEE T. on Neural Systems and Rehabilitation Eng., vol.17(4), pp. 312-321, Aug. 2009.[3] B. Gosselin et al., “A Mixed-Signal Multichip Neural Record-ing Interface with Bandwidth Reduction,” IEEE T. Biomed.Circ. Sys., vol. 3(3), pp. 129-141. June 2009.[4] A. M. Sodagar et al., “An Implantable 64-Channel WirelessMicrosystem for Single-Unit Neural Recording,” IEEE J. Sol-id-State Circ., vol. 44(9), pp. 2591-2604, Sept. 2009.[5] F. Shahrokhi et al., “The 128-Channel Fully Differential Dig-ital Integrated Neural Recording and Stimulation Interface,” inIEEE Trans. on Biomedical Circuits and Systems, vol. 4(3), pp.149-161, June 2010.[6] S. B. Lee et al., “An Inductively Powered Scalable 32-ChannelWireless Neural Recording System-on-a-Chip for Neuro-science Applications,” in IEEE ISSCC 2010, pp. 120-123. Feb.2010.[7] S. Rai et al., “A 500uW Neural Tag with 2uVrms AFE and Fre-quency-Multipying MICS/ISM FSK Transmitter,” in IEEEISSCC 2009, pp. 212-214. Feb. 2009.[8] X. Zou et al., “A 1-V 450-nW Fully Integrated ProgrammableBiomedical Sensor Interface Chip,” in IEEE J. on Solid-StateCircuits, vol. 44(4), pp. 1067-1077, April 2009.[9] R. R. Harrison and C. Charles, “A low-power low-noiseCMOS amplifier for neural recording applications”, IEEE J.Solid-State Circ., vol. 38, no. 3, pp. 958-965, June 2003.[10] J. Ruiz-Amaya et al., “A comparative study of low-noise am-plifiers for neural applications,” in Int. Conf. on Microelectron-ics (ICM 2010), pp. 327-330, Dec. 2010.[11] A. Rodríguez-Pérez et al., “A Power Efficient Neural SpikeRecording Channel with Data Bandwitdh Reduction,” in IEEEISCAS 2011, pp. 1704-1707, May 2011.[12] A. M. Kamboh and A. J. Mason, “On-chip Feature Extractionfor Spike Sorting in High Density Implantable Neural Record-ing Systems,” in IEEE BIOCAS 2010), pp. 13-16. Nov. 2010.LPctrl<1:0> 11= HPctrl<1:0> 01=0 20 40 60 80 100 120 140-0.300.3t(ms)LNA output (V)0 20 40 60 80 100 120 1400100200t(ms)ADC code32 32.5 33 33.5 34 34.5 35 35.5 36-0.2-0.100.10.2t(ms)LNA output (V)32 32.5 33 33.5 34 34.5 35 35.5 360100200t(ms)ADC code32 32.5 33 33.5 34 34.5 35 35.5 36t(ms)PGA<2>PGA<1>PGA<0>44 44.5 45 45.5 46 46.5 47-0.2-0.100.10.2t(ms)LNA output (V)44 44.5 45 45.5 46 46.5 4750100150200250t(ms)ADC code44 44.5 45 45.5 46 46.5 47t(ms)LPctrl<1>LPctrl<0>50 60 70 80 90 100 110 120 130 140-0.2-0.100.10.2t(ms)LNA output (V)50 60 70 80 90 100 110 120 130 14050100150200t(ms)ADC code50 60 70 80 90 100 110 120 130 140t(ms)HPctrl<1>HPctrl<0>Fig. 6: Chronogram of the digital calibration procedure on the typical corner: (a) ADC and LNA output, detailed views of the (a) PGA, (b) low-frequency pole and (c) high-frequency pole calibrations.(a) (b) (c)467

A self-calibration circuit for a neural spike recording channel

https://idus.us.es/bitstream/11441/90047/1/A%20Self-Calibration%20Circuit.pdf

A self-calibration circuit for a neural spike recording channel

Abstract

Similar works

Full text

Available Versions

idUS. Depósito de Investigación Universidad de Sevilla