This paper presents a 12-bit low-voltage
low-power reconfigurable Analog-to-Digital Converter
(ADC). The design employs Switched Capacitor (SC)
techniques and implements a Successive Approximation
(SA) algorithm. The ADC can be tuned to handle a large
variety of biopotential signals, with digitally selectable
resolution and input signal amplitude. It achieves 10.4-bit
of effective resolution sampling at 56kS/s, with a power
consumption below 3μW from a 1V voltage supply.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Delgado Restituto, Manuel

Medeiro Hidalgo, Fernando

Rodríguez Pérez, Alberto

Rodríguez Vázquez, Ángel Benito

English

idUS. Depósito de Investigación Universidad de Sevilla

A Low-Power Reconfigurable ADC forBiomedical Sensor InterfacesAlberto Rodríguez-Pérez, Manuel Delgado-Restituto, Fernando Medeiro and Angel Rodríguez-VázquezInstitute of Microelectronics of Seville (IMSE-CNM-CSIC) and University of SevilleEdificio IMSE-CNM, Avda. Americo Vespucio s/n, 41092-Sevilla, SPAINe-mail: alberto@imse.cnm.es Tlf.: +34 954 466 667 Fax: +34 954 466 600Abstract − This paper presents a 12-bit low-voltagelow-power reconfigurable Analog-to-Digital Converter(ADC). The design employs Switched Capacitor (SC)techniques and implements a Successive Approximation(SA) algorithm. The ADC can be tuned to handle a largevariety of biopotential signals, with digitally selectableresolution and input signal amplitude. It achieves 10.4-bitof effective resolution sampling at 56kS/s, with a powerconsumption below 3μW from a 1V voltage supply.I. INTRODUCTIONFig.1 shows the typical block diagram of abio-potential acquisition interface. It includes a band-pass low-noise amplifier (which selects and amplifiesthe signal of interest and rejects the DC offset intro-duced by the electrodes), followed by a programmablegain amplifier and then by an ADC. Commonly theADC is realized by using a Successive Approximation(SA) architecture to reduce power consumption [1-3]. Since different bio-potential signals pose differentconstraints on the block specifications, optimum oper-ation with a single system requires tunable blocks. Thecircuit in [3] incorporates programmability of both thebandpass frequency and gain of the front-end interface.However, for optimum power consumption the ADCmust be tunable as well. This paper reports a reconfig-urable SA-ADC which can adapted to differentbio-potential acquisition applications and environmen-tal conditions.SA-ADCs consist of a Sample&Hold (S&H) cir-cuit followed by a feedback loop which implements abinary search algorithm. Such a loop is composed by acomparator, a Successive Approximation Register(SAR) logic block, and a N-bit Digital-to-Analog Con-verter (DAC). Most often, and particularly for low res-olution applications (below 10bit), the DAC is realizedthrough passive, charge redistribution capacitor arrays[1-3]. In these architectures the capacitor sizes impacton the ADC resolution such that both the area occupa-tion and the power consumption increase very rapidlywith the targeted ADC resolution. This feature is dis-advantageous for programmability. Moreover, thesestructures exhibit very high sensitivity to parasiticcapacitances. Parasitics of 3% with respect to the nom-inal capacitance may induce a 1-bit degradation of theeffective resolution. This is an important drawback inmodern technologies where MiMs capacitors are beingreplaced by MoMs structures with larger parasiticcapacitances − as high as 20% of the nominal.This paper presents a 12-bit charge redistributionSA-ADC which employs active Switched-Capacitor(SC) techniques, instead of passive capacitive DACs,to implement the binary search algorithm. The ADCfollows an operation principle similar to that in [4], butonly uses a fully-differential opamp and a comparatorto reduce as much as possible the power and area con-sumptions. The ADC requires less than 3μW to obtain10.4-bit effective resolution (worst case) at 550kHzclock frequency under 1V supply. The gain of the pro-posed ADC can be programmed through a 3-bit digitalcontrol word between x1 and x8, thus allowing either torelax the specifications of the programmable gainamplifier in Fig.1 or even replace its function. TheADC resolution and the ADC conversion rate can betuned within the 6-bit to 12-bit range and within the10kS/s to 100kS/s range, respectively. Active blocksare made programmable (using a 2-bit control word) sothat their power consumptions scale in accordancewith the required resolution and conversion rate. TheADC occupies 0.12mm2 including the input gain stage.The paper is structured as follows. Section IIdescribes the architecture of the ADC. The design ofthe most critical blocks is detailed in section III. Sec-tion IV illustrates the performance of the converter.Finally, section V compares the proposed ADC withcapacitor-based charge redistribution solutions.II. ARCHITECTURE OF THE SA ADCFig.2 shows the operation principle and timingdiagram of the proposed SA-ADC, where  and are non-overlapping clocks. It consists of a S&H block,an integrator and a divide-by-two circuit. The input isfirst sampled by the S&H and then transferred to theintegrator. Afterwards, the stored voltage is comparedwith a threshold to determine the Most Significant Bit(MSB). Depending on the comparison result, voltage Fig. 1: Typical biosensor interface architecture.FromsensorsProgrammableADCDoutBandwidthControl Gain AmplifierΦ1 Φ2978-1-4244-4918-7/09/$25.00 ©2009 IEEE 253, initially set to , is either added or subtractedfrom the integrated voltage. The newly accumulatedvalue is compared again with the threshold to set thefollowing bit of the conversion. The procedure repeatsuntil the magnitude of the increments is ,where  is the target resolution.Fig.3 shows the schematic of the proposedFully-Differential (FD) SA-ADC based on this algo-rithm. Reference voltage division and S&H operationsare realized by passive SC circuits. Offset and gainerrors of the opamp are cancelled to a first order bymeans of capacitors  [5]. FD operation reducescharge injection errors, is less susceptible to com-mon-mode noise and provides a larger output voltageswing − an appealing feature for low-voltage applica-tions. Note also that, for given ADC resolution, thecapacitor count of this topology is much lower thanthat of capacitive-based DAC architectures. Hence, FDoperation does not report area penalty.Circuit operation is divided into two cyclesdenoted, respectively, as signal acquisition cycle andconversion cycle. The former starts with the samplingphase ( ) during which the input data is storedon . Additionally, the reference voltage  isstored on , the opamp offset is stored on  andthe voltages across capacitors  and  are can-celled. In the next phase,  is OFF,  is ON, andthe charge stored in  is transferred to  so thatthe differential output voltage of the integratorbecomes . Note that if  is realizedwith a digitally-programmable capacitor array, theamplitude of the ADC input signal can be made exter-nally selectable. During the next phase (  and), the sign of the integrator output voltage isdetected by means of the comparator. If , and the MSB (Most Significant Bit) of theconversion is set to “1”, otherwise, the MSB is “0”. Afterwards, the conversion cycle starts by turning-controlled switches ON. During this phase (  isOFF), assuming that , half of the chargestored on  is transferred to  and, hence, to theintegrator. Assuming that  and depending onthe value of the previous comparison, either  or is active, producing either a decrement or anincrement by  in the output voltage of the inte-grator, respectively. During the next phase  is ON(  is OFF), the sign of the stored voltage determinesthe next most significant bit and capacitor  is reset.Phases  and  are alternatively repeated until therequired N-bit digital representation is obtained. Notethat because of the charge sharing operation betweencapacitors  and , the magnitude of the incre-ments/decrements are progressively decreasing from to . Therefore, the ADC requires clock periods to complete the conversion. It isworth noting, that the resolution of the proposed archi-tecture can be easily controlled by digitally setting thenumber of clock periods during the conversion cycle.In order to minimize mismatch and charge injec-tion errors, the unity capacitor is 1pF.III. DESIGN OF THE SA-ADC BLOCKSCritical building blocks to the performance of theSA converter are the comparator and the FD opamp.  Fig. 2: Block diagram of the proposed SA A/D converter.S&HΦsVin∫Φin+Φ2ΦinS&H ÷2Φs+Φ1Φ1ΦsVref Φ2+−SARLOGICDoutΦsΦsΦinΦ2Φ1ΦLMSB LSBclkVthVAVA Vref 2⁄Vref 2N 1–⁄N Fig. 3: Simplified schematic of the proposed fully differential SC-based SA-ADC architecture.vcm vcm vcm+−ΦsΦs+Φ1Φ2Φ2ΦsΦdΦdΦ2·VcompVrefΦsΦsΦsΦsΦsΦsΦsΦsvcompVinΦsΦsΦinΦinCvarCintCintC1C1C2C2CoffCoffΦcompΦlatchΦLΦ1Φinv cmv cmΦsCvarΦinv cmv cmΦsΦs+Φ1Φ2·VcompΦ2·VcompCoffΦS 1=Cvar VrefC1 CoffCint C2ΦS ΦinCvar CintCvar Cint⁄( )Vin CvarΦin 0=Φ1 1=vin 0>vcomp 1=Φ2 Φ1C1 C2=C1 C2C2 Cint=Φ2negΦ2posVref 2⁄Φ1Φ2C2Φ2 Φ1C1 C2Vref 2⁄ Vref 2N 1–⁄N 1+254A. Fully Differential Operational AmplifierFig. 4 shows the OTA used in the integrator of theADC. It is a fully-differential class-AB two-stageMiller-compensated amplifier [3]. Class-AB operationis achieved through a push-pull output scheme(through capacitors CLS), which drives both the nMOSand pMOS transistors of the second stage of the ADC.Capacitors CM do the Miller compensation. All transis-tors work in sub-threshold region. Transistors M10 andM11 operate in deep sub-threshold region and exhibitvery high channel resistance. They are used to set thevoltage across capacitors CLS. The continuous-timecommon-mode circuitry, not shown in Fig. 4, uses aconventional two differential pair topology and con-trols the common-mode through Vcmc [8].In order to include programmability on this block,the multiplicity of transistors M1, M6 and M7 isselectable, controlling the bias current of the opampand adapting it to the required bandwidth [3]. In orderto fit conversion rates ranging from 10kS/s to 100kS/s,the GBW can be programmed from 500kHz to 5MHz,keeping 60dB DC-gain with power consumptionsranging from 400nW to 1.6μW through two bits ofcontrol.B. ComparatorDue to the fact that the ADC has to detect differ-ential voltages below 1mV, an auto-zeroed comparatorcomposed of a preamplifier and a dynamic latch is usedto accomplish the desired resolution [7]. Fig.5 showsthe structure of the comparator.The pre-amplifier uses a nMOS input differentialstructure. Auto-zeroing is achieved by closing a unitygain loop around the pre-amplifier and storing the off-set voltage on the input capacitors [7]. This stage yieldsa worst-case dynamic gain of around 40dB in 1μs,which is high enough to counteract the large input off-set of the dynamic latch. The bias current of this blockcan be also programmed to adapt its power consump-tion to the required resolution and conversion rate. Thepower consumption of the overall comparator variesfrom 250nW to 1μW.IV. SIMULATION RESULTSThe layout of the ADC, designed in ST 90-nmCMOS technology, is shown in Fig.6. Table I collectsits main characteristics obtained from post-layout sim-ulations under Process, Voltage and Temperature(PVT) variations and device mismatch.Fig.7 shows the results of a FFT analysis of theADC, operating in 12-bit mode, for a 760Hz full-scaleinput tone, assuming nominal PVT. The conversionrate is 56kS/s with a 784kHz clock frequency and 1-Vsupply. It can be observed that all the spurious arebelow 74dB and the SNDR is 64.37dB, which corre-sponds to an ENOB of 10.4bit.V. COMPARISON WITH CAPACITIVE DAC SOLUTIONSThe proposed architecture is advantageous versuscapacitive DAC-based solutions regarding power con-sumption, area occupation and sensitivity to parasitic Fig. 4: Class AB fully-differential opamp with dynamic levelshifter.in+in-VbncVcmcout+VbncCLSCMM1M2M3M4M5M7M9M11out-VbncCLSCMM6M8M10dynamic latchin+in-out+out-ΦsΦsΦlatch Fig. 5: Two-stage input offset storage comparator schematic.ΦcompTABLE I. Characteristics of the ADCResolution 6-12bitTechnology ST 90nmVoltage supply 1VConversion Rate 56kS/sENOB (1kHz input @ 1V supply) 10.4bitSNDR (1kHz input @ 1V supply) 64.37dBGain error 0.05% FSOffset error 0.1 LSBEstimated Power Consumption @ 1V supply 3μWArea 0.12mm2 Fig. 6: Layout of the SA-ADC. Fig. 7: FFT analysis in 12-bit operation mode (nominal PVT).0 5 10 15 20 25–120–100–80–60–40–200Frequency (kHZ)Magnitude (dB)SNDR = 64.37dBSFDR = 74.37dB255capacitances.Fig.8 shows the power consumption of the pro-posed SA-ADC in 12-bit configuration as a function ofthe sampling frequency. The figure also shows thepower consumptions of most commonly used capaci-tive DAC-based solutions, binary weighted [1] andsplit ones [2-3] for the same resolution. The unitarycapacitance for the capacitive DACs has been set to200fF, a typical value used for this kind of converter.Most of the power dissipation in DAC-based solutionsoccurs during the reset phase, when the capacitivearray is charged. During this phase large current spikesare drained from the supply source which puts strongerdemands on the regulatory circuitry. Alternatively, thepower consumption of the proposed solution is mainlydue to the opamp whose power consumption remainsnearly constant over the whole conversion period.Fig.9 compares the area occupation of the proposedarchitecture (without the programmable gain inputstage) with the capacitive ones. It can be seen that theproposal is more efficient in terms of area from 9-bit ofresolution onwards.Although split solutions are more efficient interms of power consumption, they are extremely sensi-tive to parasitic capacitances, as is shown in Fig.10. Inthis plot the ENOB is represented versus the parasiticcapacitance per unit capacitance, including routingparasitics. These parasitics introduce non-linear errorsin DAC-based topologies which degrade the resolutionof the converter. However, the proposed solutionremains nearly insensitive to them.VI. CONCLUSIONSA low-power, low-voltage SA-ADC based on SCtechniques has been presented. The proposed architec-ture is highly reconfigurable in terms of input gain, res-olution, and sampling rate. The power consumption isalso adaptive in accordance to the required resolutionby programming the tail current of the active blocks.This features make the ADC very suitable for wirelesssensor networks applications. Additionally, the pro-posed converter has smoother (spike-free) current con-sumption, less silicon area, and lower sensitivity toparasitic capacitances than capacitive DAC-basedSA-ADCs.VII. ACKNOWLEDGMENTSThis work was supported by the Spanish Ministryof Education & Science under grant TEC2006-03022,and the Junta de Andalucía under grant TIC-02818.REFERENCES[1] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energyADC for smart dust,” IEEE J. Solid-State Circ., vol. 38, pp.1123-1129, Jul. 2003.[2] A. Agnes, E. Bonizzoni and F. Maloberti, “Design of anUltra-Low Power SA-ADC with medium/high resolution andspeed,” in ISCAS 2008, pp. 1-4.[3] X. Zou, X. Xu, L. Yao and Y. Lian, “A 1-V 450-nW Fully Inte-grated Programmable Biomedical Sensor Interface Chip,” IEEEJ. of Solid-State Circ., vol. 44(4), pp. 1067-1077, April 2009.[4] S. Ogawa and K. Watanabe, “A Switched-Capacitor Succes-sive-Approximation A/D Converter,” IEEE Trans. Instr. andMeas., vol. 42(4), Aug. 1993.[5] K. Nagaraj, K. Singhal, T. R. Viswanathan and J. Vlach, “Reduc-tion of the finite gain effect in switched-capacitor filters,” Elec.Lett., vol. 21, pp. 644-645, Jul. 1985.[6] M. Mollazadeh, K. Murari, G. Cauwenberghs and N. Thakor,“Micropower CMOS Integrated Low-Noise Amplification, Fil-tering, and Digitazation of Multimodal Neuropotentials,” IEEETrans. Biomedical Circ. and Syst., vol. 3(1), pp. 1-10, Feb. 2009.[7] A. Rodríguez-Vázquez, et al, “Trade-offs in the design ofCMOS Comparators”, C. Toumazou et al., Trade-Offs in AnalogCircuit Design: The Designer’s Companion, pp. 407-441, Klu-wer Academic Publishers, Dordrecht (The Netherlands), 2002.[8] P. R. Gray, P. J. Hurst, S. L. Lewis and R. G. Meyer, AnalogDesign of Analog Integrated Circuits, 4th Edition. John Wiley &Sons, New York, 2001. Fig. 8: Power Consumption versus Sampling Frequency of differentcapacitive DACs and the proposed solution.1 10 100051015202530354045Sampling Frequency (kHz)Power Consumption (uW)  BinarySplitProposed Fig. 9: Area Occupation versus resolution of different capacitiveDACs and the proposed solution.6 7 8 9 10 11 120,010,1110Resolution (bits)Area Occupation (mm2)  BinarySplitProposed Fig. 10: ENOB versus parasitic capacitances of capacitive splitDAC and proposed solution.0 2 4 6 8 10 12 14 16 18 208.599.51010.51111.512Cparasitic / Cunit (%)ENOB  proposedsplit256

A low-power reconfigurable ADC for biomedical sensor interfaces

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A low-power reconfigurable ADC for biomedical sensor interfaces

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