This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.Ministerio de Ciencia e Innovación TEC2009-0844

Delgado Restituto, Manuel

Masuch, Jens

Rodríguez Pérez, Alberto

Rodríguez Rodríguez, José Antonio

Rodríguez Vázquez, Ángel Benito

English

idUS. Depósito de Investigación Universidad de Sevilla

A 64-Channel Inductively-Powered NeuralRecording Sensor ArrayAlberto Rodríguez-Pérez, Jens Masuch, José A. Rodríguez-Rodríguez, Manuel Delgado-Restituto and Ángel Rodríguez-VázquezInstitute of Microelectronics of Sevilla and University of SevillaAvda. Americo Vespucio s/n, 41092-Seville, SPAINEmail: {alberto, masuch, rodriguez, mandel, angel}@imse-cnm.csic.esAbstract—This paper reports a 64-channel inductively poweredneural recording sensor array. Neural signals are acquired,ﬁltered, digitized and compressed in the channels. Additionally,each channel implements a local auto-calibration mechanismwhich conﬁgures the transfer characteristics of the recording site.The system has two operation modes; in one case the informationcaptured by the channels is sent as uncompressed raw data; inthe other, feature vectors extracted from the detected neuralspikes are transmitted. Data streams coming from the channelsare serialized by an embedded digital processor and transferredto the outside by means of the same inductive link used forpowering the system. Simulation results show that the powerconsumption of the complete system is 377μW.I. INTRODUCTIONIn the last years, there has been a growing interest on thedesign of multichannel neural recording interfaces with wire-less transmission capabilities for the untethered measurementof brain activity [1]–[3]. These interfaces are expected to playa signiﬁcant role both in clinical (as part of therapeutic pro-cedures in patients with neurological diseases), brain-machineinterfaces and neuroscience applications. As these recordinginterfaces are implanted below the skull, the use of ultra-low power consumption techniques is mandatory, not only toprevent from harmful effects in the brain, but also to avoidthe need for batteries. Thus, by making the power dissipationlow, it becomes feasible to use energy harvesting strategies forsupplying the implant. This is illustrated in Fig. 1 in whichthe intracranial device is powered via a wireless inductive linkfrom an external unit placed on the head. The same link or adedicated one could be also employed for data transfer to suchexternal unit from where information could be communicatedto a speciﬁc hub for compiling and processing the recordedbrain activity.This paper aims to contribute to this scenario and presents amultichannel wireless neural sensor array designed in a stan-dard 0.13μm CMOS process. It is composed of 64 channelsin which neural signals are acquired, ﬁltered, digitized andoptionally compressed [4]. The system has two transmissionmodes; in one case the information captured from a selectedset of channels is transmitted as uncompressed raw data,in the other, feature vectors are extracted from the detectedneural spikes at every channel and transmitted to the externalunit for further processing. A single wireless inductive link,inspired in RFID technologies, is used both for poweringskullbrainscalpBattery-free multichannel sensorInductive linkExternal UnitUser InterfaceData StorageCentral ProcessorElectrodesFigure 1. Implanted solution of the wireless neural array.the implant and for data transfer to/from the external unit.This link uses a 40.68MHz carrier signal and employs On-Off Keying (OOK) modulation for data transfer from theexternal unit to the implant (forward link) and Load-ShiftKeying (LSK) in the reverse direction (backward link). A4MHz clock is used to send information through the backwardlink. This is enough for the implant operated in the featureextraction mode to characterize and serialize the detectedspikes even in the unlikely case all the channels ﬁre at thesame instant. Post-layout simulations show that the total powerconsumption of the system, including the recording array andthe communication protocol, is only 377μW, i.e., about oneorder of magnitude below prior art.The paper is organized as follows. The architecture of theneural sensor is detailed in Section II. Section III presents thedesign of the RF front-end, while the simulation results aregiven in Section IV. Finally, Section V ends the paper withsome conclusions.II. NEURAL SENSOR ARCHITECTUREFig. 2 shows the architecture of the proposed system.It consists of a 8x8 neural recording array, each of themserially connected to an Event-Based Processor Unit (EBPU),which stores the information generated by the channel. Thedata stored in these EBPUs are read and classiﬁed by anembedded digital processor, which also handles the timingof the implant. A communication block implements the linkto/from the external unit. Additionally, the system includes one228PGAVinBand-limitedLNAPGA + SC–based ADCHPctrlLPctrlPGActrlDirectDigitalFrequencySynthesizer(DDFS)x8BinarySearchCalibration Threshold DetectorFeature ExtractionSerial TxonSerial RxonCell ProcessorADCenx64Serial RxonEBPURegisterCounterEBPU Configx64Clock dividerData Rxon Pie DecoderCUPCell ProgramSerial Output RegisterDigital ProcessorEncoderBandgapClock Recovery BackscatterOOK DemodulatorRectifierDigital RegulatorAnalog RegulatorFigure 2. Architecture of the multichannel neural array.tunable Direct Digital Frequency Synthesizer (DDFS) per rowfor calibration purposes [5].Each channel embeds all the needed circuitry to acquire anddigitize neural waveforms including a Low Noise Ampliﬁer(LNA), a digitally tunable band-pass ﬁlter, a ProgrammableGain Ampliﬁer (PGA), an Analog-to-Digital Converter (ADC)and a local digital processor to detect neural spikes and extracttheir features. The channel architecture is similar to that in[4] but, in this version, spike detection is accomplished indigital domain and the decision threshold is adaptively updatedaccording to the noise ﬂoor of the captured signal. Further, inorder to increase the granularity of the calibration process,three control bits are used to adjust the high-pass pole of thebandpass ﬁlter.A. Modes of operationTogether with the two already mentioned transmissionmodes, denoted as signal tracking and feature extractionmodes, the system also offers a foreground calibration mode.They are brieﬂy described next.Calibration: In this mode, the transfer characteristic andgain of the recording channels are individually adjusted. Thisis done by sequentially adjusting the pass-band of the ﬁltersand the gain of the PGAs using the algorithm in [5]. First,the programming words for the high-pass (3-bit) and low-pass(2-bit) poles of the channel bandpass ﬁlter are tuned so thatits passband ranges from about 200Hz to 7kHz, correspondingto the spike spectral range. This is done for every channel byusing the output signals of the DDFSs as frequency references.As there is one DDFS per row, passband calibration is donein a column-wise manner. Afterward, every channel startscapturing neural signals at a rate of 27kS/s and the gain ofeach PGA is adjusted so that its output ﬁts into the inputdynamic range of the corresponding ADC. Digitized signalsare transmitted out column by column so that an externalobserver validates the completion of the calibration process.This is done because neural spiking is random by natureand channels can be silent for long periods. After validation,the observer can change to a different column or ﬁnish thecalibration process by applying corresponding commands.Signal Tracking: In this mode, one column/row of thearray is arbitrarily selected for neural signal monitoring whileremaining channels are disabled for power saving. Neuralsignals are acquired at a sampling rate of 27kS/s, 8-bit persample, to give an overall throughput rate of 1.92Mbps. Nodata compression is applied in this mode.Feature Extraction: In this case, the system is employed forspike detection tasks. All the 64 channels are enabled duringfeature extraction. Every detected spike is locally compressedat channel level by means of a Piece-Wise Linear (PWL)approximation of its waveform. This approximation involvesamplitude and time interval values, an results in a 47-bitrepresentation per spike, enough for sorting and clusteringpurposes [4]. During the characterization of the spike thechannel operates at a sampling rate of 90kS/s.B. Event-Based CommunicationEBPU units are the responsible for temporarily storing theinformation provided by the channels. In the calibration andsignal tracking modes, channels serialize and transfer datato the EBPUs, where information is retained until it is readout by the system digital processor. In the feature extractionmode, EBPUs not only provide storing resources but alsocontribute on the calculation of the time intervals involvedin the PWL representation of spikes. Peaking and thresholdcrossing events along spikes are transmitted to correspondingEBPUs. Such units keep track of the duration between theevents by means of counters. When spikes end, channels sendto the EBPUs the amplitude related information to completethe associated PWL feature vectors. Once vectors are gathered,they are stored in the EBPUs ready to read out. It is worthobserving this approach reduces the information transfer fromthe channels to the EBPUs by about 50%, as single eventsinstead of complete time interval measurements (coded in 8-bit words) are transmitted.The main digital processor cyclically reads the enabledEBPUs. If it is found the stored information in the EBPUis complete, the digital processor retrieves data at a 4MHzrate, builds up the transmission frame and sends this streamto the telemetry unit for wireless transmission.C. Communication ProtocolSimilar to RFID technologies, the system uses Pulse IntervalEncoding (PIE) of symbols in the forward link. Fig. 3(a)shows the symbol representations for data-0 and data-1, whichessentially differ on the duration of the high-level state.Fig. 3(b) illustrates the structure of data frames in theforward link, i.e. towards the sensor array. They are used toconﬁgure the neural recording sensor array. A forward frame229ffCRCPreamblestab RTCALCommand Data5 14 52 3Tb0PWTb1=2*Tb0PW‘0’ ‘1’a)b)Preamble CRC8 72 5Datac)opt1st cal O/M LP HPvth_opt6 322 12nd cal O/M PGAcell_selection8 32 1signal trackingO/M SP4 72 1TH VTHfeature extractionO/M S/T2 72 3other_optVADC1HPLP PGA VTH23 3 7 498 8 7 88MMMVADC28VADC8“01010101”ID CELL862ID CELLID CELL VP1 VP2 VTH 1 2 3 filler8 8 17626240fillersignal trackingfeature extractioncalibrationFigure 3. Communication protocol of the proposed system: a) PIE format,b) forward frame, c) backward frame.consists of 24-bit, including preamble (5 bit), command (14bit) and cyclic redundancy check (CRC) word (5 bit). Asshown in Fig. 3(b), the structure and parameters included inthe command word depends on the selected operation mode.Fig. 3(c) shows the structure of data frames in the backwardlink, i.e. from the sensor array to the outside. The backwardframe is 85-bit long and includes a ﬁxed 8-bit preamble“01010101”, followed by a 72-bit output data set, and com-pleted by a 5-bit CRC word. The ﬁrst 8-bit of the output dataset inform about the operation mode (2-bit) and the channelidentiﬁcation (6-bit). In the signal tracking mode, the systemcollects the sampled data in groups of eight (by column orrow, depending on the selected option), and only the ﬁrstchannel of the column/row has to be identiﬁed. In the featureextraction mode, the output data set is formed by three bytesof temporal information, two bytes of amplitude informationand 7-bit representing the applied threshold voltage. In thecalibration mode, the system generates 15-bit which inform onthe settings for the bandpass ﬁlter, PGA and threshold voltage.III. TELEMETRY UNITFig. 4 shows the schematics of the power and data telemetryunit. It is based on inductive link techniques and operates in theworldwide available ISM band centered at 40.68MHz. Data re-ception employs (OOK) modulation whereas data transmissionis accomplished by modulating the amplitude of the carrierby means of a switchable antenna matching network drivenby the digital processor. In this latter case, the modulationdepth is less than 50% and the output data is encoded usinga Manchester encoder.Not shown in the ﬁgure, the telemetry unit also includesa timing recovery circuit which extracts the 4MHz clock ofModulator Rectifierdoutdemodulator rectifierdem_endinDemodulatorVrectManchesterEncoderInductive CouplingExternal UnitFigure 4. Schematic of the telemetry front-end.4.6mm4mmF C S G400mDIGITALPROCESSORLNA,Band-PassFilterPADPGA - ADC400 mFigure 5. Layout of the multichannel neural sensor.the system from the incoming RF signal, which is also used tomodulate the backward link. This is accomplished by means ofdivide by 2 circuits based on single-transistor-clocked dynamiclatches [6].The telemetry unit also includes a power managementcircuitry which harvest energy from the inductive link usinga rectiﬁer. Analog and digital supply lines of 1.2V are ob-tained from corresponding regulators, while a bandgap circuitgenerates the analog voltage references. The efﬁciency of therectiﬁer is 60% at 1mW RF input power.IV. POST-LAYOUT RESULTSFig. 5 shows the layout of the proposed system. It hasbeen designed in a 6M2P 0.13μm standard CMOS technology.Each channel includes an internal pad for ﬂip-chip connectionto a microelectrode. For the sake of testability, the channelinput nodes can be also accessed from an external padring.Clamp cells are placed along the chip periphery to protectthe microelectrode nodes from ESD damages. The systemoccupies 18.4mm-sq.Fig. 6 illustrates the operation of the adaptive thresholdalgorithm implemented in the local digital processor of thechannels. The signal-to-noise ratio of the neural signal hasbeen intentionally varied to better appreciate the evolution ofthe threshold detection level. As can be seen, the algorithmreacts in less than 0.5s to changes in the background noise.Fig. 7 illustrates the system operation in the feature extrac-tion mode. Dots represent the spikes detected by the neural2300 5 10 15 20 25 30050100150200250time (s)CodeFigure 6. Adaptive threshold voltage algorithm: Neural signal (blue), voltagethreshold (red), noise level (yellow).0 1 20100200time (ms)200 202 204 20601020304050600 100 200 300 4000204060Cellnumbertime (ms) time (ms)C11C25C39C63C33C51C1 C25 C39 C63 C33 C51201 202 203 204 205 2062 31tspikeCode0 1 20100200time (ms)2 31tspikeCode11101011 00111001 0100000 00000110 00010000 0001010000011011 11001000 0100000 00000111 00010001 00010111Vp1 Vp2 Vth 1 2 3Vp1 Vp2 Vth 1 2 3199.5 201.5200.52 4 206205time (ms)Figure 7. Data output stream under feature extraction mode.array in a time slot of 500ms. Once a spike is detected in achannel and its PWL representation derived (47-bits, as ﬁgure7 illustrates), the feature vector is stored in the associatedEBPU. The main digital processor cyclically reads the EBPUsevery 237μs. Considering the 85-bit length of the backwardframe detailed in Section II, the system requires 21.25μs totransmit the information of one spike at 4MHz. Therefore, wecan calculate the maximum possible delay by summing up thedelay of the EBPU reading and the transmission delay, whichresults 258.25μs. This is much lower than a typical spikeduration (around 2ms) and, of course, much lower than thetime basis for ﬁring occurrences. It means, that no informationis lost not even in the unlikely case all the channels ﬁre at thesame instant (only a small delay no larger than about 10% theduration of a spike could be observed in some of the records).The performance of most of the blocks comprised in thechannels (LNA, ﬁlter and ADC) were measured and reportedin [4]. The new channel implementation in this paper alsoincludes an additional digital processor which, together withthe needed buffers to communicate along the array, risethe power consumption per channel to 4.54μW. From thesimulated power consumption it can be extrated that most ofthe power is consumed by the neural channels (290.56μW).The main digital processor and EBPUs, which make extensiveuse of clock gating and clock frequency division techniques,consumes 40μW (5μW of them dissipated by leakage cur-rents). Bandgap references, regulators and current conveyorsTable IPERFORMANCE SUMMARY AND COMPARISON[1] [2] [3] This workTechnology (μm) 0.18 0.18 0.13 0.13Supply voltage (V) 1.8 1.8 / 1 0.5 1.2Number of channels 16 32 16 64Total power (μW) 680 325 18 377Power / channel (μW) 42.5 10.1 1.13 5.9High pass freq. (Hz) 100 350 400 200Low pass freq. (kHz) 9.2 12 7.5 6.9Input ref. noise (μVrms) 5.4 5.4 5.32 3.8NEF 4.9 4.4 3.09 2.16ENOB (bits) 7 7.65 7.32 7.65Sampling freq. (kS/s) 30 31.25 30 27 / 90Data bitrate reduction Yes No No Yesconsume 32μW. The clock recovery block, the Manchesterencoder and the demodulator require, respectively, 12.5μW,1.5μW and 400nW. All in all, the total power consumption ofthe system sums 377μW.Table I summarizes the performance of the neural recordingsystem and compares it with some state-of-the-art works. Notethat the presented work presents one of the lowest powerdissipation per channel, even though it is the only one thatincludes a wireless communication circuitry.V. CONCLUSIONSA 64-channel neural array with embedded data reductiontechniques, fabricated in a standard CMOS 130nm process,has been presented. Inspired by RFID systems, an inductivelink is used for both powering the implant and transferringinformation to/from an external unit placed on the head. Adistributed digital signal processing approach, with tasks atchannel- and array levels, has been found an efﬁcient solutionfor reducing the power consumption of the SoC and sim-plifying communications through the array. The total powerconsumption of the system has been estimated in 377μW froma nominal voltage supply of 1.2V, i.e., about one order ofmagnitude below prior art.ACKNOWLEDGMENTSThis work has been supported by the Spanish Ministry ofScience & Innovation under grant TEC2009-08447 and the2007-2013 FEDER Program.REFERENCES[1] B. Gosselin et al., “A mixed-signal multichip neural recording interfacewith bandwidth reduction,” IEEE Trans. Biomed. Circuits, vol. 3, no. 3,pp. 129–141, 2009.[2] W. Wattanapanitch and R. Sarpeshkar, “A low-power 32-channel digitallyprogrammable neural recording integrated circuit,” Biomedical Circuitsand Systems, IEEE Transactions on, vol. 5, no. 6, pp. 592–602, 2011.[3] L. Wen-Sin, Z. Xiaodan, and L. Yong, “A 0.5-v 1.13uw/channel neu-ral recording interface with digital multiplexing scheme,” in ESSCIRC(ESSCIRC), 2011 Proceedings of the, pp. 219–222.[4] A. Rodriguez-Perez, J. Ruiz-Amaya, M. Delgado-Restituto, andA. Rodriguez-Vazquez, “A low-power programmable neural spike detec-tion channel with embedded calibration and data compression,” IEEETrans. Biomed. Circuits, vol. 6, no. 2, pp. 87 –100, april 2012.[5] A. Rodriguez-Perez et al., “A self-calibration circuit for a neural spikerecording channel,” in Proc. IEEE Biomed. Circ. and Systems Conf., nov.2011, pp. 464 –467.[6] J. Yuan and C. Svensson, “New single-clock cmos latches and ﬂipﬂopswith improved speed and power savings,” IEEE J. Solid-State Circ.,vol. 32, no. 1, pp. 62–69, 1997.231

A 64-channel inductively-powered neural recording sensor array

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A 64-channel inductively-powered neural recording sensor array

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idUS. Depósito de Investigación Universidad de Sevilla