Design of an ATM LAN Access Switch Based on IEEE P1355

An ATM LAN Access Switch (ALAX) based on IEEE P1355 is being designed at the Laboratory for Advanced Switching Technologies (LAST) as a collaborative project by a research team which consists of the Protocol Engineering Center (PEC) of Electronics and Telecommunications Research Institute (ETRI) of Korea, Institute for Systems Research (ISR) of the University of Maryland at College Park (UMCP) and Modacom Co., Ltd. of Korea. The main function of the ALAX is to provide interfaces among different legacy communication networks and the ATM world. The design objective of the ALAX system is to achieve an excellent performance/cost ratio while simplifying the overall process of systems engineering, rather than to achieve the highest possible speeds. In this paper, some of the architectural issues involved in the ALAX design are discussed

IEEE 1355-Based Architecture for an ATM Switch: A Case for Onboard Switching and Processing

The recent evolution of the communication scenario has profound implications for the role of communication satellites within the communication infrastructure. Indeed, it raises the possibility that the satellite be viewed not merely as a repeater but rather as a network node in its own right in a hopefully integrated space/terrestrial network. We draw attention to the new IEEE 1355 Standard for Heterogeneous Inter-Connect as a possible platform to support several onboard processing functions, including onboard communications and onboard ATM switching. The IEEE 1355 is a new serial bus standard which enables high- performance, scalable, modular, parallel systems to be constructed with low system integration cost. This IEEE 1355- based approach can satisfy many of the requirements of onboard communications and onboard ATM switching, e.g., size, flexibility, reliability, fault-tolerance, and high communication processing speeds. This is made possible by using the highly integrated 1355 chipsets and performing protocol processing with multiple transputers in parallel. The IEEE 1355 approach also allows for easy expandability owing to its inherent design modularity

ATM/LAN Access Switch (ALAX): System Architecture

This document contains the hardware information for the ATM LAN Access Switch (ALAX) that was done as a collaborative research and development effort by the Institute for Systems Research at the University of Maryland, College Park, Protocol Engineering Center in Electronics and Telecommunications Research Institute, and Modacom Co., Ltd. of Korea.<P

Report on Selected Standardization Activities of the IEEE BASC and of the ATM Forum

This document describes the standardization activities which were performed during the first year period of the joint project named ﲁ Standardization and Research Project on an ATM/B-ISDN Switching Fabric System that is being jointly performed by Protocol Engineering Center (PEC) of Electronics and Telecommunications Research Institute (ETRI), Institute for Systems Research (ISR) of the University of Maryland at College Park (UMCP) and Modacom Co., Ltd. These standardization activities are related to the IEEE Bus Architecture Standards Committee (BASC) meetings and ATM Forum Meetings. This document also provides the general information about the IEEE Standards meetings and ATM Forum Standards meetings.<P

OPNET Simulation Model of the ALAX

When this project wsa undertaken, the ALAX system was designed but was not built yet. Because it was too complicated for us to easily predict the detailed behavior of the system before we built it, we decided to use the OPNET simulation to evaluate the ALAX system before it was built. The performance of the ALAX could be predicted by analyzing the results of the OPNET simulation, and the optimal architecture of the ALAX developed by devising the proper number of transputers and the proper packet buffer size of the ALAX system.<P

ALAX- A P1355-Based Architecture for An ATM LAN Access Switch, with Application to ATM Onboard Switching

We draw attention to the new IEEE P1355 Standard for Heterogeneous InterConnect as a possible platform to support several onboard processing functions, including onboard communications and onboard ATM switching. The main features of IEEE P1355 are illustrated through a discussion of the basic principles and protocol architecture of ALAX, the ATM LAN Access Switch, currently under design in the Laboratory for Advanced Switching Technologies at the University of Maryland, College Park

KrasP34R and KrasT58I mutations induce distinct RASopathy phenotypes in mice.

Somatic KRAS mutations are highly prevalent in many cancers. In addition, a distinct spectrum of germline KRAS mutations causes developmental disorders called RASopathies. The mutant proteins encoded by these germline KRAS mutations are less biochemically and functionally activated than those in cancer. We generated mice harboring conditional KrasLSL-P34Rand KrasLSL-T58I knock-in alleles and characterized the consequences of each mutation in vivo. Embryonic expression of KrasT58I resulted in craniofacial abnormalities reminiscent of those seen in RASopathy disorders, and these mice exhibited hyperplastic growth of multiple organs, modest alterations in cardiac valvulogenesis, myocardial hypertrophy, and myeloproliferation. By contrast, embryonic KrasP34R expression resulted in early perinatal lethality from respiratory failure due to defective lung sacculation, which was associated with aberrant ERK activity in lung epithelial cells. Somatic Mx1-Cre-mediated activation in the hematopoietic compartment showed that KrasP34R and KrasT58I expression had distinct signaling effects, despite causing a similar spectrum of hematologic diseases. These potentially novel strains are robust models for investigating the consequences of expressing endogenous levels of hyperactive K-Ras in different developing and adult tissues, for comparing how oncogenic and germline K-Ras proteins perturb signaling networks and cell fate decisions, and for performing preclinical therapeutic trials

Design of a multiprocessor high-bandwidth communication gateway based on a protocol processor pool architecture

The proliferation of the high-speed networks is expected to occur in the near future. However, the available implementations of gateways are not able to deal with these high data rates and become the bottleneck of the communication systems. Therefore, we need a high-speed gateway that can interconnect various kinds of high-speed networks;The Multiprocessor High-bandwidth Communication Gateway based on a Protocol Processor Pool Architecture which we have named HIPAMG and satisfies the requirements of the high-speed networks is proposed in this dissertation. HIPAMG connects FDDI stations and BISDN stations in multi-media environment. A new design concept called Protocol Processor Pool Architecture is proposed and implemented in the HIPAMG. After completing the gateway design, the performance of the gateway is simulated using the OPNET graphic simulator and the design parameters are tuned to optimize the gateway design.</p