Fabrication and characterization of memory devices based on nanoparticles

Tese de doutoramento, Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2013The objective of this study is to understand the electrical properties of non-volatile memories based on metal oxide nanoparticles embedded into an insulating polymer matrix. These memories are classified as resistive random access memories (RRAM), as they undergo resistive switching between well-defined conductance states when submitted to a voltage pulse. A number of memory devices were fabricated and studied using electrical techniques. Current-voltage characteristics were studied as a function of the ambient atmosphere and temperature. The dynamic electrical behaviour was probed using triangular voltage profiles with different scan rates, transient techniques and electrical noise techniques. Electrical measurements were complemented with morphological characterization. Important outcomes of this thesis are the following: It was shown that adsorbed moisture on the surface of the devices causes resistive switching. This type of resistive switching can lead to very high on/off ratios, and therefore it is not reliable. Silver oxide nanoparticles undergo an electroforming process similar to a soft-breakdown mechanism as reported for binary oxides. A model that explains the basic features of the electroforming mechanism was proposed. After the electroforming, the devices show resistance switching properties with a high on/off ratio (> 104), good retention time, and programming endurance. A resistive switching mechanism was proposed. The model assumes that during electroforming a percolation network of micro conducting paths (filaments) is established between the electrodes. The creation and rupture of these micro-paths is responsible for the changes in conductance. Results from this study indicate that nanostructured thin films made of silver oxide nanoparticles embedded in an insulating polymer show an electrical behaviour like the bulk oxide based memory structures. The planar structures present the advantage of being programmed in multi-resistance levels suggesting a very interesting finding that may pave the way to achieve a multi-bit memory deviceO objetivo desta tese foi estudar as propriedades elétricas de componentes electrónicos fabricados com nanopartículas de metálicas. Este tipo de memoria é designado por memorias resistivas porque mudam a sua resistência elétrica através da aplicação de um tensão elétrica. Este componente é conhecido por “memristor”. Um conjunto de memorias resistivas foi fabricado e caracterizado. Nomeadamente foram realizadas um conjunto de medidas elétricas em diferentes ambientes (vácuo e atmosfera ambiente) e em função da temperatura para obter informação sobre os mecanismos de transporte electrónico e sobre a comutação elétrica da resistência. As memorias fabricadas tem um elevado hiato entre os estados resistivos (> 104), são não-voláteis e robustas, tendo sido testadas com mais de mil ciclos de programação entre os estados resistivos. Esta tese propõe um modelo para explicar as variações de resistência elétrica. O modelo assume que as partículas de prata oxidam e formam um óxido de prata. Durante o processo de formação da memoria, o elevado campo elétrico aplicado leva a ruptura dielétrica controlada do óxido e forma defeitos eletricamente ativos. Esta rede de defeitos gera micro-caminhos para a condução elétrica ou filamentos. As mudanças de resistência elétrica são causadas pela criação/ruptura deste filamentos. Os resultados desta tese indicam que as mudanças de resistência elétrica em filmes nanoestruturados com nanopartículas metálicas são semelhantes as observadas em estruturas resistivas com base em filmes finos óxidos como o dióxido de titânio (TiO2) e o óxido de alumínio (Al2O3) entre outros. Os “memristors” fabricadas neste tese são estruturas planares. O objectivo inicial foi ter um instrumento de caracterização mais simples que a estrutura convencional em sanduiche. No entanto a estrutura planar permite também obter vários níveis de resistência elétrica sugerindo que pode funcionar como memorias “multi-bit”

A neural network approach towards generalized resistive switching modelling

Funding: This research was funded by FEDER funds through the COMPETE 2020 Programme and National Funds through FCT—Portuguese Foundation for Science and Technology under project number DFA/BD/8335/2020. Publisher Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland.Resistive switching behaviour has been demonstrated to be a common characteristic to many materials. In this regard, research teams to date have produced a plethora of different devices exhibiting diverse behaviour, but when system design is considered, finding a ‘one-model-fits-all’ solution can be quite difficult, or even impossible. However, it is in the interest of the community to achieve more general modelling tools for design that allows a quick model update as devices evolve. Laying the grounds with such a principle, this paper presents an artificial neural network learning approach to resistive switching modelling. The efficacy of the method is demonstrated firstly with two simulated devices and secondly with a 4 µm2 amorphous IGZO device. For the amorphous IGZO device, a normalized root-mean-squared error (NRMSE) of 5.66 × 10−3 is achieved with a [2, 50, 50, 1] network structure, representing a good balance between model complexity and accuracy. A brief study on the number of hidden layers and neurons and its effect on network performance is also conducted with the best NRMSE reported at 4.63 × 10−3 . The low error rate achieved in both simulated and real-world devices is a good indicator that the presented approach is flexible and can suit multiple device types.publishersversionpublishe

Memristors using solution-based IGZO nanoparticles

Solution-based indium-gallium-zinc oldde (IGZO) nanoparticles deposited by spin coating have been investigated as a resistive switching layer in metal-insulator-metal structures for nonvolatile memory applications. Optimized devices show a bipolar resistive switching behavior, low programming voltages of +/- 1 V, on/off ratios higher than 10, high endurance, and a retention time of up to 104 s. The better performing devices were achieved with annealing temperatures of 200 degrees C and using asymmetric electrode materials of titanium and silver. The physics behind the improved switching properties of the devices is discussed in terms of the oxygen deficiency of IGZO. Temperature analysis of the conductance states revealed a nonmetallic filamentary conduction. The presented devices are potential candidates for the integration of memory functionality into low-cost System-on-Panel technology.National Funds through FCT - Portuguese Foundation for Science and Technology [UID/CTM/50025/2013, SFRH/BDP/99136/2013]; FEDER [POCI-01-0145-FEDER-007688]info:eu-repo/semantics/publishedVersio

Operational stability of solution based zinc tin oxide/SiO2 thin film transistors under gate bias stress

In this study, we report solution-processed amorphous zinc tin oxide transistors exhibiting high operational stability under positive gate bias stress, translated by a recoverable threshold voltage shift of about 20% of total applied stress voltage. Under vacuum condition, the threshold voltage shift saturates showing that the gate-bias stress is limited by trap exhaustion or balance between trap filling and emptying mechanism. In ambient atmosphere, the threshold voltage shift no longer saturates, stability is degraded and the recovering process is impeded. We suggest that the trapping time during the stress and detrapping time in recovering are affected by oxygen adsorption/desorption processes. The time constants extracted from stretched exponential fitting curves are approximate to 10(6) s and 10(5) s in vacuum and air, respectively. (C) 2015 Author(s).FEDER through COMPETE 2020 Programme; European Communities 7th Framework Programme (i-FLEXIS project) [ICT-2013-10-611070]; National Funds through FCT-Portuguese Foundation for Science and Technology [UID/CTM/50025/2013, EXCL/CTM-NAN/0201/2012]info:eu-repo/semantics/publishedVersio

Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors

The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons. Published by AIP Publishing

Intrinsic and extrinsic resistive switching in a planar diode based on silver oxide nanoparticles

Resistive switching is investigated in thin-film planar diodes using silver oxide nanoparticles capped in a polymer. The conduction channel is directly exposed to the ambient atmosphere. Two types of switching are observed. In air, the hysteresis loop in the current–voltage characteristics is S-shaped. The high conductance state is volatile and unreliable. The switching is mediated by moisture and electrochemistry. In vacuum, the hysteresis loops are symmetric, N-shaped and exhibit a negative differential resistance region. The conductance states are non-volatile with good data retention, programming cycling endurance and large current modulation ratio. The switching is attributed to electroforming of silver oxide clusters

Towards Sustainable Crossbar Artificial Synapses with Zinc-Tin Oxide

UIDB/50025/2020-2023In this article, characterization of fully patterned zinc-tin oxide (ZTO)-based memristive devices with feature sizes as small as 25 µm2 is presented. The devices are patterned via lift-off with a platinum bottom contact and a gold-titanium top contact. An on/off ratio of more than two orders of magnitude is obtained without the need for electroforming processes. Set operation is a current controlled process, whereas the reset is voltage dependent. The temperature dependency of the electrical characteristics reveals a bulk-dominated conduction mechanism for high resistance states. However, the charge transport at low resistance state is consistent with Schottky emission. Synaptic properties such as potentiation and depression cycles, with progressive increases and decreases in the conductance value under 50 successive pulses, are shown. This validates the potential use of ZTO memristive devices for a sustainable and energy-efficient brain-inspired deep neural network computation.publishersversionpublishe

Opto-electronic characterization of electron traps upon forming polymer oxide memory diodes

Metal-insulator-polymer diodes where the insulator is a thin oxide (Al2O3) layer are electroformed by applying a high bias. The initial stage is reversible and involves trapping of electrons near the oxide/polymer interface. The rate of charge trapping is limited by electron transport through the polymer. Detrapping of charge stored can be accomplished by illuminating with light under short-circuit conditions. The amount of stored charge is determined from the optically induced discharging current transient as a function of applied voltage and oxide thickness. When the charge density exceeds 8 1017/m2, an irreversible soft breakdown transition occurs to a non-volatile memory diode

Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.publishersversionpublishe

The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

The dynamic response of a non-volatile, bistable resistive memory fabricated in the form of Al2O3/polymer diodes has been probed in both the off- and on-state using triangular and step voltage profiles. The results provide insight into the wide spread in switching times reported in the literature and explain an apparently anomalous behaviour of the on-state, namely the disappearance of the negative differential resistance region at high voltage scan rates which is commonly attributed to a “dead time” phenomenon. The off-state response follows closely the predictions based on a classical, two-layer capacitor description of the device. As voltage scan rates increase, the model predicts that the fraction of the applied voltage, Vox , appearing across the oxide decreases. Device responses to step voltages in both the off- and on-state show that switching events are characterized by a delay time. Coupling such delays to the lower values of Vox attained during fast scan rates, the anomalous observation in the on-state that, device currents decrease with increasing voltage scan rate, is readily explained. Assuming that a critical current is required to turn off a conducting channel in the oxide, a tentative model is suggested to explain the shift in the onset of negative differential resistance to lower voltages as the voltage scan rate increases. The findings also suggest that the fundamental limitations on the speed of operation of a bilayer resistive memory are the time- and voltage-dependences of the switch-on mechanism and not the switch-off process