The use of arbuscular mycorrhizal inoculum in viticulture is not always positive: a systematic review

For more than 70 years, the scientific literature has demonstrated that arbuscular mycorrhizal fungi (AMF) have positive effects on plant growth and stress tolerance. However, AMF have only been widely implemented in agricultural systems in the last decade. Recent reviews indicate AMF are key to the sustainability of viticulture. To explore the universality of the positive effects of AMF inoculation on grapevines, we created a database of the results from 30 publications that performed 169 experiments comparing the development of grapevine plants inoculated with AMF against control vines. We calculated inoculation dependence, as ID = ((mean of inoculated treatment – mean of control)/mean of inoculated treatment) * 100), to compare the effects of AM inoculation on the growth of grapevine plants between different experiments. In most studies, the experimental conditions differed significantly from commercial conditions, since 75% of the studies were conducted under greenhouse conditions and 71.8% of studies compared the growth of inoculated plants with plants growing in a sterilized substrate. High variability was observed in the ID of different response variables, be-tween the various rootstocks tested, and between different species compositions of AMF inoculum, demonstrating that the effects of mycorrhizal inoculation in vineyard growth are highly context dependent. This study demonstrates further research is required to characterize the effects of AMF under field conditions. Moreover, this work indicates that specific trials are needed to determine the effect of particular mycorrhizal strains on individual rootstocks under specific growing conditions before the use of AMF can be recommended to vine-growers

Historic exposure to herbivores, not constitutive traits, explains plant tolerance to herbivory in the case of two Medicago species (Fabaceae)

Altres ajuts: Direcció General de Política Universitària i Recerca (Govern de les Illes Balears) FPI/1925/2016Mechanisms that allow plants to survive and reproduce after herbivory are considered to play a key role in plant evolution. In this study, we evaluated how tolerance varies in species with different historic exposure to herbivores considering ontogeny. We exposed the range-restricted species Medicago citrina and its closely related and widespread species M. arborea to one and two herbivory simulations (80 % aerial biomass loss). Physiological and growth parameters related to tolerance capacity were assessed to evaluate constitutive values (without herbivory) and induced tolerance after damage. Constitutive traits were not always related to greater tolerance, and each species compensated for herbivory through different traits. Herbivory damage only led to mortality in M. citrina; adults exhibited root biomass loss and increased oxidative stress after damage, but also compensated aerial biomass. Despite seedlings showed a lower death percentage than adults after herbivory in M. citrina, they showed less capacity to recover control values than adults. Moderate tolerance to M. arborea herbivory and low tolerance to M. citrina is found. Thus, although the constitutive characteristics are maintained in the lineage, the tolerance of plants decreases in M. citrina. That represents how plants respond to the lack of pressure from herbivores in their habitat

Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor

© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a reduced instruction set computing (RISC) microprocessor. We have carried out an exhaustive reliability assessment by using very-high-speed-integrated-circuit hardware description language (VHDL)-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.This work was supported by the Spanish Government under the Research Project TIN2009-13825 and by the Universitat Politecnica de Valencia under the Project SP20120806. Associate Editor: L. Cui.Gracia-Morán, J.; Baraza Calvo, JC.; Gil Tomás, DA.; Saiz-Adalid, L.; Gil, P. (2014). Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor. IEEE Transactions on Reliability. 63(1):144-153. https://doi.org/10.1109/TR.2014.2299711S14415363

Reducing the Overhead of BCH Codes: New Double Error Correction Codes

[EN] The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors.This research was supported in part by the Spanish Government, project TIN2016-81075-R, by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032, and by the Institute of Information and Communication Technologies (ITACA).Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2020). Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics. 9(11):1-14. https://doi.org/10.3390/electronics9111897S114911Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748Xinmiao, Z. (2017). VLSI Architectures for Modern Error-Correcting Codes. doi:10.1201/b18673Bose, R. C., & Ray-Chaudhuri, D. K. (1960). On a class of error correcting binary group codes. Information and Control, 3(1), 68-79. doi:10.1016/s0019-9958(60)90287-4Chen, P., Zhang, C., Jiang, H., Wang, Z., & Yue, S. (2015). High performance low complexity BCH error correction circuit for SSD controllers. 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). doi:10.1109/edssc.2015.7285089IEEE 802.3-2018 - IEEE Standard for Ethernethttps://standards.ieee.org/standard/802_3-2018.htmlH.263: Video Coding for Low Bit Rate Communicationhttps://www.itu.int/rec/T-REC-H.263/enVangelista, L., Benvenuto, N., Tomasin, S., Nokes, C., Stott, J., Filippi, A., … Morello, A. (2009). Key technologies for next-generation terrestrial digital television standard DVB-T2. IEEE Communications Magazine, 47(10), 146-153. doi:10.1109/mcom.2009.52738222013 ITRS—International Technology Roadmap for Semiconductorshttp://www.itrs2.net/2013-itrs.htmlIbe, E., Taniguchi, H., Yahagi, Y., Shimbo, K., & Toba, T. (2010). Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule. IEEE Transactions on Electron Devices, 57(7), 1527-1538. doi:10.1109/ted.2010.2047907Gil-Tomás, D., Gracia-Morán, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability, 52(11), 2837-2846. doi:10.1016/j.microrel.2012.06.004Neubauer, A., Freudenberger, J., & Khn, V. (2007). Coding Theory. doi:10.1002/9780470519837Morelos-Zaragoza, R. H. (2006). The Art of Error Correcting Coding. doi:10.1002/0470035706Naseer, R., & Draper, J. (2008). DEC ECC design to improve memory reliability in Sub-100nm technologies. 2008 15th IEEE International Conference on Electronics, Circuits and Systems. doi:10.1109/icecs.2008.4674921Saiz-Adalid, L.-J., Gracia-Moran, J., Gil-Tomas, D., Baraza-Calvo, J.-C., & Gil-Vicente, P.-J. (2019). Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. IEEE Access, 7, 151131-151143. doi:10.1109/access.2019.2947315Saiz-Adalid, L.-J., Gil-Vicente, P.-J., Ruiz-García, J.-C., Gil-Tomás, D., Baraza, J.-C., & Gracia-Morán, J. (2013). Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. Computer Safety, Reliability, and Security, 178-189. doi:10.1007/978-3-642-40793-2_17Saiz-Adalid, L.-J., Reviriego, P., Gil, P., Pontarelli, S., & Maestro, J. A. (2015). MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(10), 2332-2336. doi:10.1109/tvlsi.2014.2357476Gracia-Moran, J., Saiz-Adalid, L. J., Gil-Tomas, D., & Gil-Vicente, P. J. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2132-2142. doi:10.1109/tvlsi.2018.2837220Cadence: Computational Software for Intelligent System Designhttps://www.cadence.comStine, J. E., Castellanos, I., Wood, M., Henson, J., Love, F., Davis, W. R., … Jenkal, R. (2007). FreePDK: An Open-Source Variation-Aware Design Kit. 2007 IEEE International Conference on Microelectronic Systems Education (MSE’07). doi:10.1109/mse.2007.44NanGate FreePDK45 Open Cell Libraryhttp://www.nangate.com/?page_id=232

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

[EN] Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction-double error detection (SEC-DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.This research was supported in part by the Spanish Government, project TIN2016-81,075-R, and by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032.Baraza Calvo, JC.; Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2020). Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. Electronics. 9(12):1-30. https://doi.org/10.3390/electronics9122074S130912International Technology Roadmap for Semiconductors (ITRS)http://www.itrs2.net/2013-itrs.htmlJeng, S.-L., Lu, J.-C., & Wang, K. (2007). A Review of Reliability Research on Nanotechnology. IEEE Transactions on Reliability, 56(3), 401-410. doi:10.1109/tr.2007.903188Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K., & Toba, T. (2010). Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule. IEEE Transactions on Electron Devices, 57(7), 1527-1538. doi:10.1109/ted.2010.2047907Boussif, A., Ghazel, M., & Basilio, J. C. (2020). Intermittent fault diagnosability of discrete event systems: an overview of automaton-based approaches. Discrete Event Dynamic Systems, 31(1), 59-102. doi:10.1007/s10626-020-00324-yConstantinescu, C. (2003). Trends and challenges in VLSI circuit reliability. IEEE Micro, 23(4), 14-19. doi:10.1109/mm.2003.1225959Bondavalli, A., Chiaradonna, S., Di Giandomenico, F., & Grandoni, F. (2000). Threshold-based mechanisms to discriminate transient from intermittent faults. IEEE Transactions on Computers, 49(3), 230-245. doi:10.1109/12.841127Contant, O., Lafortune, S., & Teneketzis, D. (2004). Diagnosis of Intermittent Faults. Discrete Event Dynamic Systems, 14(2), 171-202. doi:10.1023/b:disc.0000018570.20941.d2Sorensen, B. A., Kelly, G., Sajecki, A., & Sorensen, P. W. (s. f.). An analyzer for detecting intermittent faults in electronic devices. Proceedings of AUTOTESTCON ’94. doi:10.1109/autest.1994.381590Gracia-Moran, J., Gil-Tomas, D., Saiz-Adalid, L. J., Baraza, J. C., & Gil-Vicente, P. J. (2010). Experimental validation of a fault tolerant microcomputer system against intermittent faults. 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN). doi:10.1109/dsn.2010.5544288Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2), 147-160. doi:10.1002/j.1538-7305.1950.tb00463.xSaiz-Adalid, L.-J., Gil-Vicente, P.-J., Ruiz-García, J.-C., Gil-Tomás, D., Baraza, J.-C., & Gracia-Morán, J. (2013). Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. Computer Safety, Reliability, and Security, 178-189. doi:10.1007/978-3-642-40793-2_17Frei, R., McWilliam, R., Derrick, B., Purvis, A., Tiwari, A., & Di Marzo Serugendo, G. (2013). Self-healing and self-repairing technologies. The International Journal of Advanced Manufacturing Technology, 69(5-8), 1033-1061. doi:10.1007/s00170-013-5070-2Maiz, J., Hareland, S., Zhang, K., & Armstrong, P. (s. f.). Characterization of multi-bit soft error events in advanced SRAMs. IEEE International Electron Devices Meeting 2003. doi:10.1109/iedm.2003.1269335Schroeder, B., Pinheiro, E., & Weber, W.-D. (2011). DRAM errors in the wild. Communications of the ACM, 54(2), 100-107. doi:10.1145/1897816.1897844BanaiyanMofrad, A., Ebrahimi, M., Oboril, F., Tahoori, M. B., & Dutt, N. (2015). Protecting caches against multi-bit errors using embedded erasure coding. 2015 20th IEEE European Test Symposium (ETS). doi:10.1109/ets.2015.7138735Kim, J., Sullivan, M., Lym, S., & Erez, M. (2016). All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory. 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). doi:10.1109/isca.2016.60Hwang, A. A., Stefanovici, I. A., & Schroeder, B. (2012). Cosmic rays don’t strike twice. ACM SIGPLAN Notices, 47(4), 111-122. doi:10.1145/2248487.2150989Gil-Tomás, D., Gracia-Morán, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability, 52(11), 2837-2846. doi:10.1016/j.microrel.2012.06.004Plasma CPU Modelhttps://opencores.org/projects/plasmaArlat, J., Aguera, M., Amat, L., Crouzet, Y., Fabre, J.-C., Laprie, J.-C., … Powell, D. (1990). Fault injection for dependability validation: a methodology and some applications. IEEE Transactions on Software Engineering, 16(2), 166-182. doi:10.1109/32.44380Gil-Tomas, D., Gracia-Moran, J., Baraza-Calvo, J.-C., Saiz-Adalid, L.-J., & Gil-Vicente, P.-J. (2012). Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection. IEEE Design & Test of Computers, 29(6), 66-73. doi:10.1109/mdt.2011.2179514Rashid, L., Pattabiraman, K., & Gopalakrishnan, S. (2010). Modeling the Propagation of Intermittent Hardware Faults in Programs. 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing. doi:10.1109/prdc.2010.52Amiri, M., Siddiqui, F. M., Kelly, C., Woods, R., Rafferty, K., & Bardak, B. (2016). FPGA-Based Soft-Core Processors for Image Processing Applications. Journal of Signal Processing Systems, 87(1), 139-156. doi:10.1007/s11265-016-1185-7Hailesellasie, M., Hasan, S. R., & Mohamed, O. A. (2019). MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/iscas.2019.8702589Mittal, S. (2018). A survey of FPGA-based accelerators for convolutional neural networks. Neural Computing and Applications, 32(4), 1109-1139. doi:10.1007/s00521-018-3761-1Intel Completes Acquisition of Alterahttps://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/#gs.mi6ujuAMD to Acquire Xilinx, Creating the Industry’s High Performance Computing Leaderhttps://www.amd.com/en/press-releases/2020-10-27-amd-to-acquire-xilinx-creating-the-industry-s-high-performance-computingKim, K. H., & Lawrence, T. F. (s. f.). Adaptive fault tolerance: issues and approaches. [1990] Proceedings. Second IEEE Workshop on Future Trends of Distributed Computing Systems. doi:10.1109/ftdcs.1990.138292Gonzalez, O., Shrikumar, H., Stankovic, J. A., & Ramamritham, K. (s. f.). Adaptive fault tolerance and graceful degradation under dynamic hard real-time scheduling. Proceedings Real-Time Systems Symposium. doi:10.1109/real.1997.641271Jacobs, A., George, A. D., & Cieslewski, G. (2009). Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space. 2009 International Conference on Field Programmable Logic and Applications. doi:10.1109/fpl.2009.5272313Shin, D., Park, J., Park, J., Paul, S., & Bhunia, S. (2017). Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Design & Test, 34(6), 84-93. doi:10.1109/mdat.2016.2615844Silva, F., Muniz, A., Silveira, J., & Marcon, C. (2020). CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC. 2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI). doi:10.1109/sbcci50935.2020.9189901Mukherjee, S. S., Emer, J., Fossum, T., & Reinhardt, S. K. (s. f.). Cache scrubbing in microprocessors: myth or necessity? 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings. doi:10.1109/prdc.2004.1276550Saleh, A. M., Serrano, J. J., & Patel, J. H. (1990). Reliability of scrubbing recovery-techniques for memory systems. IEEE Transactions on Reliability, 39(1), 114-122. doi:10.1109/24.52622X9SRA User’s Manual (Rev. 1.1)https://www.manualshelf.com/manual/supermicro/x9sra/user-s-manual-1-1.htmlChishti, Z., Alameldeen, A. R., Wilkerson, C., Wu, W., & Lu, S.-L. (2009). Improving cache lifetime reliability at ultra-low voltages. Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42. doi:10.1145/1669112.1669126Datta, R., & Touba, N. A. (2011). Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. 29th VLSI Test Symposium. doi:10.1109/vts.2011.5783773Kim, J., Lim, J., Cho, W., Shin, K.-S., Kim, H., & Lee, H.-J. (2016). Adaptive Memory Controller for High-performance Multi-channel Memory. JSTS:Journal of Semiconductor Technology and Science, 16(6), 808-816. doi:10.5573/jsts.2016.16.6.808Yuan, L., Liu, H., Jia, P., & Yang, Y. (2015). Reliability-Based ECC System for Adaptive Protection of NAND Flash Memories. 2015 Fifth International Conference on Communication Systems and Network Technologies. doi:10.1109/csnt.2015.23Zhou, Y., Wu, F., Lu, Z., He, X., Huang, P., & Xie, C. (2019). SCORE. ACM Transactions on Architecture and Code Optimization, 15(4), 1-25. doi:10.1145/3291052Lu, S.-K., Li, H.-P., & Miyase, K. (2018). Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). doi:10.1109/iolts.2018.8474118Chen, J., Andjelkovic, M., Simevski, A., Li, Y., Skoncej, P., & Krstic, M. (2019). Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems. 2019 22nd Euromicro Conference on Digital System Design (DSD). doi:10.1109/dsd.2019.00080Wang, X., Jiang, L., & Chakrabarty, K. (2020). LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection. 2020 IEEE 38th VLSI Test Symposium (VTS). doi:10.1109/vts48691.2020.9107600Ebrahimi, H., & G. Kerkhoff, H. (2018). Intermittent Resistance Fault Detection at Board Level. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). doi:10.1109/ddecs.2018.00031Ebrahimi, H., & Kerkhoff, H. G. (2020). A New Monitor Insertion Algorithm for Intermittent Fault Detection. 2020 IEEE European Test Symposium (ETS). doi:10.1109/ets48528.2020.9131563Hsiao, M. Y. (1970). A Class of Optimal Minimum Odd-weight-column SEC-DED Codes. IBM Journal of Research and Development, 14(4), 395-401. doi:10.1147/rd.144.0395Benso, A., & Prinetto, P. (Eds.). (2004). Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation. Frontiers in Electronic Testing. doi:10.1007/b105828Gracia, J., Saiz, L. J., Baraza, J. C., Gil, D., & Gil, P. J. (2008). Analysis of the influence of intermittent faults in a microcontroller. 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. doi:10.1109/ddecs.2008.4538761ZC702 Evaluation Board for the Zynq-7000 XC7Z020 SoChttps://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pd

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

(c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.[EN] Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.This work was supported in part by the Spanish Government under Project TIN2016-81075-R, and in part by the Primeros Proyectos de Investigacion, Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), Valencia, Spain, under Project PAID-06-18 20190032.Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2019). Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. IEEE Access. 7:151131-151143. https://doi.org/10.1109/ACCESS.2019.2947315S151131151143

Life-threatening lithium-induced diabetes insipidus after colonic surgery

Colonic surgery is associated with major disturbances to patients’ fluid balance as aresult of pre-operative starvation, intra-operative blood loss, insensible losses, andpost-operative ‘third space’ losses. In the post-operative period, junior surgeons arewell trained to manage oliguria, but have little experience of the management ofpost-operative polyuria. Nephrogenic diabetes insipidus occurs in 12% of patientson lithium therapy and may present in the immediate post-operative period withmassive polyuria, profound dehydration and life threatening hypernatraemia, aspatients are unable to ingest large volumes of fluid orally. We report two cases, onelife threatening, of lithium induced nephrogenic diabetes insipidus (LINDI) whichpresented in the early postoperative period after emergency colonic surgery whilstthe patients were denied oral intake. The first patient attained a peak serum sodiumconcentration of 185mmol/l and required ventilation after a respiratory arrest. Wesuggest any surgical patient who describes a history of bipolar disorder or lithiumtherapy should be questioned directly to ascertain confirmatory features of LINDI,and have post-operative polyuria treated with aggressive fluid replacement

Studying the effects of intermittent faults on a microcontroller

As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. The complexity of manufacturing processes, producing residues and parameter variations, together with special aging mechanisms, may increase the presence of such faults. This work presents a case study of the impact of intermittent faults on the behavior of a commercial microcontroller. In order to carry out an exhaustive reliability assessment, the methodology used lies in VHDL-based fault injection technique. In this way, a set of intermittent fault models at logic and register transfer abstraction levels have been generated and injected in the VHDL model of the system. From the simulation traces, the occurrences of failures and latent errors have been logged. The impact of intermittent faults has been also compared to that got when injecting transient and permanent faults. Finally, some injection experiments have been reproduced in a RISC microprocessor and compared with those of the microcontroller. © 2012 Elsevier Ltd. All rights reserved.This work has been funded by the Spanish Government under the Research Project TIN2009-13825.Gil Tomás, DA.; Gracia-Morán, J.; Baraza Calvo, JC.; Saiz-Adalid, L.; Gil Vicente, PJ. (2012). Studying the effects of intermittent faults on a microcontroller. Microelectronics Reliability. 52(11):2837-2846. https://doi.org/10.1016/j.microrel.2012.06.004S28372846521

¿Se asocia el consumo de refrescos azucarados con la composición corporal? Estudio transversal en adolescentes españoles

Objectives: Published data about the association between the consumption of sweetened soft-drinks (SSD) and obesity in childhood are controversial and still inconsistent. In addition, data are lacking in the Spanish population. The purpose of this study was therefore, to explore the cross-sectional association between body composition- related parameters and SSD consumption in Spanish adolescents. Subjects and methods: A representative sample of 1,523 adolescents (768 boys and 755 girls), with complete dietary data as well as anthropometric measurements, were included in this study. Weight, height, waist circumferences, and 6 skinfolds were measured, and BMI and percentage body fat were calculated. From a 24h dietary recall the subjects were grouped in 3 groups according to their SSD consumption: 1) Non-consumers (0 g of SSD consumption); 2) Moderate consumption (< 336 g/day of SSD, equivalent to the average SSD portion size); and 3) High consumption (> 336 g/day of SSD). Results: 67% males and 75% females did not consume any SSD the day before the dietary recall interview. Males consumed more SSD than females. Regarding the association between SSD consumption and measures of obesity, no difference was observed between the three groups of SSD consumption in any of the anthropometric measurement, BMI or body fat. Conclusion: As no association was present between SSD consumption and obesity in our cross-sectional study we suggest that dietary patterns and habits as well as lifestyle factors such as physical activity should be present when examining cross-sectional or longitudinal relationships with obesity. Multidisciplinary intervention studies are crucial when trying to develop solutions against the increasing obesity epidemic.Objetivos: Los datos publicados sobre la asociación entre el consumo de refrescos azucarados (SSD) y la obesidad en la infancia son controvertidos y todavía inconsistentes. Además, estos datos son muy escasos en la población española. Por ello, el propósito de este estudio ha sido estudiar la asociación entre los parámetros relacionados con la composición corporal y el consumo de SSD en adolescentes españoles. Sujetos y métodos: Se ha realizado el estudio en una muestra de 1.523 adolescentes (768 chicos y 755 chicas) que tenían cumplimentados los datos dietéticos y los parámetros antropométricos (peso, altura, circunferencias de cintura, y 6 pliegues). Se calculó el IMC y el porcentaje de grasa corporal. La dieta ha sido calculada a partir de un recordatorio de 24h. Los sujetos fueron divididos en grupos dependiendo de la cantidad de SSD que consumían: 1) No consumidores (0 g de consumo SSD); 2) Consumo moderado (< 336 g/día de SSD, equivalente a una bebida al día de SSD); y 3) Consumo alto (> 336 g/día de SSD). Resultados: El 67% de los varones y el 75% de las mujeres indican no consumir este tipo de bebidas el día anterior a la encuesta. Los varones en general consumieron más SSD que las mujeres. En cuanto a la asociación entre consumo SSD y medidas antropométricas y de composición corporal, no se encontraron diferencias significativas entre los tres grupos de estudio en los parámetros antropométricos, IMC o grasa corporal. Conclusión: Dado que no se ha encontrado en este estudio ninguna asociación entre el consumo de SSD y la obesidad, sugerimos que los patrones y hábitos dietarios así como los factores del estilo de vida, y la actividad física, deberían tenerse en cuenta al examinar las relaciones transversales o longitudinales con la obesidad, y que los estudios de intervención multidisciplinar son cruciales cuando se trata de desarrollar soluciones contra el incremento de una epidemia como la obesidad.The AVENA study was supported by Spanish Ministry of Health (00/0015) and by grants from the Spanish Higher Sports Council (05/UPB32/01, 09/UPB31/03 and 13/UPB20/04), the Spanish Ministry of Education (AP2003-2128 and AP2004-2745), Coca-Cola, Panrico SA, Madaus SA and Procter & Gamble SA

Cabra i forest: la qualitat dels recursos del bosc per a la cabra mallorquina

&#091;cat&#093; S’ha analitzat la composició química, en termes de proteïna, fibres i digestibilitat, de les principals espècies vegetals presents a les pinedes i matollars de Mallorca o a la dieta de les cabres assilvestrades que hi pasturen. Els resultats mostren que els recursos alimentaris per les cabres en aquests ambients són de moderada a baixa qualitat, variant molt entre espècies. D’aquest fet es conclou que la pressió de pastura per part de les cabres es reparteix per l’ampli grup d’espècies perennes que formen aquests boscos i matollars, i això és d’interès en la prevenció d’incendis forestals.&#091;eng&#093; The chemical composition, in terms of protein, fibers and digestibility, has been analyzed of the main plant species present in the pine forests and scrubs of Mallorca or in the diet of feral goats that graze on it. The results show that dietary resources for goats in these environments are moderate to low quality, varying greatly between species. It is concluded that pasture pressure by goats is spread over the large group of perennial species that form these forests and scrubland, and this is of interest in the prevention of forest fires