Metrics for fast, low-cost adders in FPGA

In this paper several adder design techniques that probed to be very effective in full-custom integrated circuit design are presented as well as the conclusions regarding its implementation on FPGA. Particularly, in this work, Xilinx XC4000E family is selected as target technology and results achieved without using dedicated carry logic present in these devices are evaluated. This paper aims to substantiate the fact that these techniques indeed reduce delay time in other technologies than full custom design and from these results decide if it is worth trying implementations using XC4000E dedicated carry logic.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

Composite materials calculation using HPC-based multiscale technique

Calculating the behavior of large composite material structures still demanding large computational effort. The solu-tion proposed to tackle the problem is to combine multi-scale homogenization methods with the high performance computa-tional techniques available. This PhD work aims to implement inside the Alya HPC-code a multi-scale algorithm capable of solving this kind of problems in an efficient and accurate way

Efecto de diferentes concentraciones de Taninos sobre la flora microbiana ruminal y en la degradabilidad in vitro del forraje de alfalfa

Tesis (Maestría en Ciencias en Producción Animal) UANLUANLhttp://www.uanl.mx

Metrics for FIR Filters based on distributed arithmetic in FPGA

In this paper, metrics regarding different architectures for distributed arithmetic based FIR filters in FPGA are presented. Main filter parameters are described as well as diverse design techniques applied: pipelining, bit-serial, digit-serial y bit-parallel. Each filter description was written in VHDL at RTL level. For achieving this goal no relative location (rloc) technique was used what redounds on more generic and expensive designs than those available through Core Generator tool. Implementation has been carried out over FPGAs belonging to Xilinx Virtex II family.Eje: IV - Workshop de procesamiento distribuido y paraleloRed de Universidades con Carreras en Informática (RedUNCI

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