Global heat balance and heat uptake in potential temperature coordinates

The representation of ocean heat uptake in Simple Climate Models used for policy advice on climate change mitigation strategies is often based on variants of the one-dimensional Vertical Advection/Diffusion equation (VAD) for some averaged form of potential temperature. In such models, the effective advection and turbulent diffusion are usually tuned to emulate the behaviour of a given target climate model. However, because the statistical nature of such a ``behavioural" calibration usually obscures the exact dependence of the effective diffusion and advection on the actual physical processes responsible for ocean heat uptake, it is difficult to understand its limitations and how to go about improving VADs. This paper proposes a physical calibration of the VAD that aims to provide explicit traceability of effective diffusion and advection to the processes responsible for ocean heat uptake. This construction relies on the coarse-graining of the full three-dimensional advection diffusion for potential temperature using potential temperature coordinates. The main advantage of this formulation is that the temporal evolution of the reference temperature profile is entirely due to the competition between effective diffusivity that is always positive definite, and the water mass transformation taking place at the surface, as in classical water mass analyses literature. These quantities are evaluated in numerical simulations of present day climate and global warming experiments. In this framework, the heat uptake in the global warming experiment is attributed to the increase of surface heat flux at low latitudes, its decrease at high latitudes and to the redistribution of heat toward cold temperatures made by diffusive flux

Features of Mild-to-Moderate COVID-19 Patients with Dysphonia

Introduction To explore the prevalence of dysphonia in European patients with mild-to-moderate COVID-19 and the clinical features of dysphonic patients. Methods The clinical and epidemiological data of 702 patients with mild-to-moderate COVID-19 were collected from 19 European Hospitals. The following data were extracted: age, sex, ethnicity, tobacco consumption, comorbidities, general and otolaryngological symptoms. Dysphonia and otolaryngological symptoms were self-assessed through a 4-point scale. The prevalence of dysphonia, as part of the COVID-19 symptoms, was assessed. The outcomes were compared between dysphonic and non-dysphonic patients. The association between dysphonia severity and outcomes was studied through Bayesian analysis. Results A total of 188 patients were dysphonic, accounting for 26.8% of cases. Females developed more frequently dysphonia than males (p=0.022). The proportion of smokers was significantly higher in the dysphonic group (p=0.042). The prevalence of the following symptoms was higher in dysphonic patients compared with non-dysphonic patients: cough, chest pain, sticky sputum, arthralgia, diarrhea, headache, fatigue, nausea and vomiting. The severity of dyspnea, dysphagia, ear pain, face pain, throat pain and nasal obstruction was higher in dysphonic group compared with non-dysphonic group. There were significant associations between the severity of dysphonia, dysphagia and cough. Conclusion Dysphonia may be encountered in a quarter of patients with mild-to-moderate COVID-19 and should be considered as a symptom list of the infection. Dysphonic COVID-19 patients are more symptomatic than non-dysphonic individuals. Future studies are needed to investigate the relevance of dysphonia in the COVID-19 clinical presentation

A way to build efficient carry-skip adders

International audienceA way is presented to obtain efficient carry-skip adders, built with blocks of different sizes in VLSI technologies. Some results for two-level carry-skip adders are given, and the optimization problem is reduced to a geometrical problem that is solved by means of an algorithm easily implemented on a microcomputer. An example of the realization of such an adder is presented

A divided decoder-matrix (DDM) structure and its application to a 8 kb GaAs MESFET ROM

ISBN: 078033583XThis paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 mu m-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW

A low-power high storage capacity structure for GaAs MESFET ROM

ISBN: 0818680997Gallium Arsenide (GaAs) is used in the design of high speed systems; however, it is difficult or impossible to realize high-capacity ROMs, because of subthreshold currents and an unacceptable power dissipation. This paper describes a new approach which overcomes the above problems and allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. In addition, this approach improves the noise margin of the DCFL gate with the increase of the fan-in. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 mu m-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW

A low-power GaAs flip-flop

This paper describes a low-power high speed flip-flop in Gallium Arsenide (GaAs) called PCLF for Pseudo-Complementary Logic Flip-Flop. The PCLF offers attractive power saving without performance degradation and is fully compatible with existing FET logic families. It can be efficiently used in the VLSI ICs, as well as in multigabit/second SSI or MSI ICs. As an example a D-flip-flop, T-flip-flop and a 1/8 divider have been designed and fabricated, verifying the expected low power dissipation