La nueva política como anunciantes en la Derecha Española: VOX y las elecciones de 2018 y 2019

This paper has tried to identify and interpret the use of all the means used by the extreme right-wing party VOX to get its message across to its audiences. In this case, a division will be made between classic and new media, paying special attention to the use of social networks, and identifying the target audiences that have been addressed. The results achieved will be analysed and the communicational causes that may have influenced them will be sought. All the research is limited space-temporarily to Spain in the years 2018 and 2019.En este trabajo se ha intentado identificar e interpretar la utilización de todos los medios utilizados por parte del partido de derecha extrema VOX para hacer llegar su mensaje a sus públicos. En este caso se hará una división entre medios clásicos y nuevos medios, prestando especial atención a la utilización de las redes sociales, e identificando los públicos objetivos a los que se ha dirigido. Se analizará los resultados alcanzados y se buscará las causas comunicacionales que hayan podido incidir en los mismos. Toda la investigación esa enclavada espacio – temporalmente a España en los años 2018 y 2019

Dimensión comunicacional de la numismática en España 1886-1939, Monarquía, Repúpublica y Guerra: sátira, publicidad y propaganda

Dimensión comunicacional de la Numismática a través de de 53 años de la historia de España con diferentes regímenes y situaciones políticas, llegando a convertirse en un medio de comunicación de masas y a la vez en un medio radical parásito que da voz a los marginados. A su vez se descubre la presencia de una modalidad numismática como son los jetones que sólo buscan una comunicación publicitaria y comercialDepartamento de Historia Moderna, Contemporánea, de América, Periodísmo y Comunicación Audiovisual y Publicida

Respuestas de los consumidores a los hoteles certificados medioambientalmente: el efecto moderador de la conciencia medioambiental sobre la formación de intenciones comportamentales

Este estudio desarrolla un modelo que explora la relación entre las prácticas verdes, la imagen verde, la conciencia medioambiental y las intenciones comportamentales de los clientes en un contexto hotelero certificado. Para testar empíricamente el modelo propuesto se realizaron 502 encuestas personales a clientes hoteleros en España. Los resultados muestran como las percepciones de los clientes sobre las prácticas verdes tienen un efecto directo y positivo en la imagen verde de las compañías hoteleras. Al mismo tiempo, esta imagen influye directa y positivamente sobre las intenciones de comportamiento de los clientes hacia los hoteles certificados medioambientalmente. También se demuestra que cuanto mayor sea la conciencia medioambiental de los consumidores, mayor será su intención de hospedarse, realizar comentarios positivos y pagar una prima por alojarse en hoteles certificados. Por último, la conciencia medioambiental ejerce un efecto moderador sobre la relación causal entre la imagen verde y las intenciones comportamentales.This study develops a model that investigates the relationship among green practices, green image, environmental consciousness and the behavioral intentions of customers in a certified hotel context. The study examines the direct and the moderating role of environmental consciousness in the formation of behavioral intentions based on green initiatives. To test the proposed model empirically, 502 personal surveys of hotel customers were conducted in Spain. The findings show that customer perceptions of green practices have a positive direct effect on a hotel´s green image. At the same time, this environmental image has positive direct effects on customer behavioral intentions towards certified hotels. The authors also found that the higher the environmental consciousness of consumers, the greater their intention to stay, to spread positive word-of-mouth and pay a premium for environmentally-certified hotels. Finally, consumer environmental consciousness also exerts a moderating effect on the causal relationship between green image and behavioral intentions

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from d(c) x q to 5 x q, and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from dc x q to 5 x q. This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm(2), which is 3.9 more efficient than the best solution found in the literature.This work was supported by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion through Formacion de Profesorado Universitario (FPU) under Grant AP2010-5178.Lacruz Jucht, JO.; García Herrero, FM.; Valls Coquillat, J. (2015). Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(11):2676-2679. https://doi.org/10.1109/TVLSI.2014.2377194S26762679231

One minimum only trellis decoder for non-binary low-density parity-check codes

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 ${rm mm}^{2}$ and 16.10 ${rm mm}^{2}$ after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order.This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universitat Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion under Grant AP2010-5178. David Declercq has been funded by the Institut Universitaire de France for this project. This paper was recommended by Associate Editor Z. Zhang.Lacruz, JO.; García Herrero, FM.; Valls Coquillat, J.; Declercq, D. (2015). One minimum only trellis decoder for non-binary low-density parity-check codes. IEEE Transactions on Circuits and Systems I: Regular Papers. 62(1):177-184. https://doi.org/10.1109/TCSI.2014.2354753S17718462

Los titulares en la comunicación escrita: diferencias y semejanzas entre los periódicos en papel y los nuevos modelos (versiones web y redes sociales)

Memoria ID-070. Ayudas de la Universidad de Salamanca para la innovación docente, curso 2018-2019

Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error correction. Unfortunately, the complexity of NB-LDPC decoders is still too high for practical applications, especially for the check node (CN) processing, which limits the maximum achievable throughput. Although a great effort has been made in the recent literature to overcome this disadvantage, the proposed decoders are still not ready for high-speed implementations for high-order fields. In this paper, a simplified trellis min max algorithm is proposed, where the CN messages are computed in a parallel way using only the most reliable information. The proposed CN algorithm is implemented using a horizontal layered schedule. The overall decoder architecture has been implemented in a 90-nm CMOS process for a ((N=837) and (K=726)) NB-LDPC code over GF(32), achieving a throughput of 660 Mb/s at nine iterations based on postlayout results. This decoder increases hardware efficiency compared with the existing recent solutions for the same code.This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916; in part by the Universitat Politecnica de Valencia, Gandia, Spain, under Grant PAID-06-2012-SP20120625; and in part by the Institut Universitaire de France, Rennes, France. The work of F. Garcia-Herrero was supported in part by the Spanish Ministerio de Educacion under Grant AP2010-5178 and in part by the Institute Universitaire de France.Lacruz Jucht, JO.; García Herrero, FM.; Declercq, D.; Valls Coquillat, J. (2015). Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(9):1783-1792. https://doi.org/10.1109/TVLSI.2014.2344113S1783179223

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396

Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm

© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher than GF(16). To overcome this drawback, we propose an approximation for the Trellis Min-Max algorithm which allows us to reduce the number of exchanged messages between check node and variable node compared to previous proposals from literature. On the other hand, we reduce the complexity in the check-node processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90nm CMOS technology for the (837,723) NB-LDPC code over GF(32) and the (1536,1344) over GF(64), achieving an area saving of 16% and 36% for the check-node and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 Gbps and 1.26 Gbps, which outperforms the state-of-the-art of high-rate decoders with high GF order from literature.This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and Grant TEC2012-38558-C02-02 and in part by Generalitat Valenciana under Grant GV/2014/011.Lacruz, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2016). Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-11. https://doi.org/10.1109/TVLSI.2016.2514484S11