İbn-i Sina ve Hayyam:büyük Türk filozofunun büyük İran şairi tarafından tercüme edilmiş bir eseri meydana çıkarıldı

Taha Toros Arşivi, Dosya No: 2-İbn-i SinaUnutma İstanbul projesi İstanbul Kalkınma Ajansı'nın 2016 yılı "Yenilikçi ve Yaratıcı İstanbul Mali Destek Programı" kapsamında desteklenmiştir. Proje No: TR10/16/YNY/010

Empowering a helper cluster through data-width aware instruction selection policies

Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. helper cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit helper cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; helper cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on averagePeer ReviewedPostprint (published version

Fuse: A technique to anticipate failures due to degradation in ALUs

This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.Peer ReviewedPostprint (published version

Retrospective comparison of flot and modified dcf as first-line chemotherapy in metastatic gastric adenocarcinoma

Background: The aim of our study was to compare the efficacy and the safety of the FLOT and the modified DCF (mDCF) regimens in patients with metastatic gastric (GC) and gastroesophageal junction (GEJ) adenocarcinoma as first-line treatment. Methods: The medical records of 72 patients were retrospectively reviewed. Survivals and hematological adverse events of the patients were examined. Factors affecting survivals were analyzed in univariate analysis. A multivariate analysis was performed with the factors contributing to survivals in univariate analysis. Results: The median PFS (mPFS) was 10.1 months (95% CI, 6.8-13.4) in the FLOT arm (n = 33) and 7.4 months (95% CI, 9.1-21.6) in the mDCF arm (n = 39) (p = 0.041). The median OS (mOS) was 12.9 months (95% CI, 9.7-16.1) in the FLOT arm and 15.4 months (95% CI, 9.1-21.6) in the mDCF arm (p = 0.622). It was found that all grade neutropenia was 51.3% vs. 72.7% (p = 0.063), febrile neutropenia was 8.3% vs. 6.3% (p = 0.743), and thrombocytopenia was 48.7% vs. 51.5% (p = 0.813) in the FLOT and mDCF arms, respectively. Anemia was 59% in the FLOT arm and 100% in the mDCF arm (p < 0.001). Grade 3-4 anemia was 7.7% in the FLOT arm and 24.2% in the mDCF arm (p = 0.052). Discussion: It was shown that the mPFS was significantly increased in the FLOT arm compared to the mDCF arm as the first-line treatment in patients with metastatic GC and GEJC. Hematological adverse events were more favorable in the FLOT arm than in the mDCF arm

Depressive symptomatology among university students in Denizli, Turkey: Prevalence and sociodemographic correlates

Aim: To determine overall and subgroup prevalence of depressive symptomatology among university students in Denizli, Turkey during the 1999-2000 academic year, and to investigate whether sociodemographic factors were associated with depressive symptoms in university students. Methods: A stratified probability sample of 504 Turkish university students (296 male, 208 female) was used in a cross-sectional study. Data were obtained by self-administered questionnaire, including questions on sociodemographic characteristics and problem areas. The revised Beck Depression Inventory (BDI) was used to determine depressive symptoms of the participants. BDI scores 17 or higher were categorized as depressive for logistic regression analysis. Student t-test and linear regression were used for continuous data analysis. Results: Out of all participants, 26.2% had a BDI score 17 or higher. The prevalence of depressive symptoms increased to 32.1% among older students, 34.7% among students with low socioeconomic status, 31.2% among seniors, and 62.9% among students with poor school performance. The odds ratio of depressive symptoms was 1.84 (95% confidence interval [CI], 1.03-3.28) in students with low socioeconomic status and 7.34 (95% CI, 3.36-16.1) in students with poor school performance in the multivariate logistic model. The participants identified several problem areas: lack of social activities and shortage of facilities on the campus (69.0%), poor quality of the educational system (54.8%), economic problems (49.3%), disappointment with the university (43.2%), and friendship problems (25.9%). Conclusions: Considering the high frequency of depressive symptoms among Turkish university students, a student counseling service offering mental health assistance is necessary. This service should especially find the way to reach out to poor students and students with poor school performance

Refueling: Preventing wire degradation due to electromigration

Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing the amount of current flowing in both directions of a wire. It can significantly extend a wire's lifetime while reducing the chip area devoted to wires.Peer ReviewedPostprint (published version

Impact of parameter variations on circuits and microarchitecture

Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.Peer ReviewedPostprint (published version

Can we trust undervolting in FPGA-based deep learning designs at harsh conditions?

As more Neural Networks on Field Programmable Gate Arrays (FPGAs) are used in a wider context, the importance of power efficiency increases. However, the focus on power should never compromise application accuracy. One technique to increase power efficiency is reducing the FPGAs' supply voltage ("undervolting"), which can cause accuracy problems. Therefore, careful design-time considerations are required for correct configuration without hindering the target accuracy. This fact becomes especially important for autonomous systems, edge-computing, or data-centers. This study reveals the impact of undervolting in harsh environmental conditions on the accuracy and power efficiency of the convolutional neural network benchmarks. We perform the comprehensive testing in a calibrated infrastructure at controlled temperatures (between -40C and 50C) and four distinct humidity levels (40%, 50%, 70%, 80%) for off-the-shelf FPGAs. We show the voltage guard-band shift with temperature is linear and propose new reliable undervolting designs providing a 65% increase in power efficiency (GOPS/W).Peer ReviewedPostprint (author's final draft

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.Comment: To appear at the DSN 2020 conferenc

Reducing soft errors through operand width aware policies

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. As a faster but less fault tolerant alternative to ECC and parity, we offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of different data-holding components of a processor. On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in the first level data cache across all Spec2K. In other structures such as the immediate field of the issue queue, an average error detection rate of 64 percent is achieved.Peer ReviewedPostprint (published version