Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology

This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB OpA general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach

Reducing the environmental impact of surgery on a global scale: systematic review and co-prioritization with healthcare workers in 132 countries

Abstract Background Healthcare cannot achieve net-zero carbon without addressing operating theatres. The aim of this study was to prioritize feasible interventions to reduce the environmental impact of operating theatres. Methods This study adopted a four-phase Delphi consensus co-prioritization methodology. In phase 1, a systematic review of published interventions and global consultation of perioperative healthcare professionals were used to longlist interventions. In phase 2, iterative thematic analysis consolidated comparable interventions into a shortlist. In phase 3, the shortlist was co-prioritized based on patient and clinician views on acceptability, feasibility, and safety. In phase 4, ranked lists of interventions were presented by their relevance to high-income countries and low–middle-income countries. Results In phase 1, 43 interventions were identified, which had low uptake in practice according to 3042 professionals globally. In phase 2, a shortlist of 15 intervention domains was generated. In phase 3, interventions were deemed acceptable for more than 90 per cent of patients except for reducing general anaesthesia (84 per cent) and re-sterilization of ‘single-use’ consumables (86 per cent). In phase 4, the top three shortlisted interventions for high-income countries were: introducing recycling; reducing use of anaesthetic gases; and appropriate clinical waste processing. In phase 4, the top three shortlisted interventions for low–middle-income countries were: introducing reusable surgical devices; reducing use of consumables; and reducing the use of general anaesthesia. Conclusion This is a step toward environmentally sustainable operating environments with actionable interventions applicable to both high– and low–middle–income countries

Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology

This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB OpA general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach