Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation silicon carbide (SiC) Power MOSFETs under unclamped inductive switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their aging under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development

Individual device active cooling for enhanced system-level power density and more uniform temperature distribution

This paper provides a method of individual device active cooling system to balance the temperature distribution of system-level power density. 3L-ANPC GaN inverter was used to test and prove the feasibility of it in using multi-level systems

GaN HEMT gate-driver for achieving high power converter integration levels

This work proposes a solution for implementing an isolated gate driver for GaN HEMTs based on the previous topology for SiC power MOSFETs. The isolation of the gate driver is realised by the single transformer topology with double winding in the secondary side. The Bi-level HF Amplitude Modulation scheme is retained to avoid the core saturation as well as providing simultaneously both the switching signal and the required gate power in the secondary side which ensures the full range duty ratio. The reconstruction of the original PWM signal is optimised using a simple hysteresis comparing scheme, which is the Schmitt Trigger circuit, to avoid sudden turn-on or turn-off. The experiment result shows that the Schmitt Trigger circuit could effectively avoid the sudden turn-on or turn-off but it might have some negative effect on the accuracy of duty circle. Finally, the feasibility of the gate driver is demonstrated with the PGA26E19BA GaN device with optimised final power stage

Avalanche ruggedness of parallel SiC power MOSFETs

© 2018 Elsevier Ltd The aim of this paper is to investigate the impact of electro-thermal device parameter spread on the avalanche ruggedness of parallel silicon carbide (SiC) power MOSFETs representative of multi-chip layout within an integrated power module. The tests were conducted on second generation 1200 V, 36 A–80 mΩ rated devices. Different temperature-dependent electrical parameters were identified and measured for a number of devices. The influence of spread in measured parameters was investigated experimentally during avalanche breakdown transient switching events and important findings have been highlighted

Experimental demonstration of an optimised PWM scheme for more even device electro-thermal stress in a 3-Level ANPC GaN inverter

GaN device as one potential power electronics device has been gained much attention recently. One of the power conversion systems, ANPC inverter using GaN HEMT is potentially considered to be prospective usage of low loss and high efficiency. In this work, we demonstrate one optimised PWM scheme aims at balancing the device electro-thermal stress based on Parma PWM to control 3-Level ANPC GaN inverter. The method is to decrease the loss for switches account for the large loss and increase the loss for switches with less thermal stress initially. The simulation and experimental results prove the effectiveness of the optimised PWM in controlling the loss distribution

Modeling environmental ageing in masonry strengthened with composites

The effects of environmental ageing due to rising damp and salt crystallization on composite strengthening systems, e.g. fiber reinforced polymer (FRP) and fiber reinforced cementitious matrix (FRCM), bonded to masonry substrates are still scarcely known. Although few laboratory tests have been recently conducted to this aim, very limited information is available. In this paper, the simulation of accelerated weathering/ageing cycles of masonry strengthened with composites is proposed by means of a multiphase model which accounts for salt transport and crystallization. This multiphase model is implemented together with ad hoc boundary conditions and a restart analysis procedure which attempt to reproduce the repetition of weathering cycles (composed of a wetting phase in a saline solution and a drying phase in the oven). Laboratory accelerated weathering tests on masonry specimens strengthened with lime mortar-based FRCM are numerically reproduced. Additional information on the salt crystallization process within the specimen is obtained along with the weathering procedure. Further numerical insights are shown and compared for different strengthening systems, i.e. cement mortar-based FRCM and FRP. Different salt crystallization patterns in the specimens with different strengthening systems are observed and discussed

SiC power MOSFETs performance, robustness and technology maturity

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics

High temperature pulsed-gate robustness testing of SiC power MOSFETs

© 2015 Elsevier Ltd. Silicon Carbide (SiC) gate oxide reliability still remains a crucial issue and is amongst the important consideration factors when it comes to the implementation of SiC MOS-based devices within industrial power electronic applications. Recent studies have emerged assessing the gate oxide reliability of SiC MOSFETs. Such studies are needed in order to fully understand the properties of SiC/SiO2 interface which is currently holding back the industry from fully utilising the superior features that SiC may offer. This paper aims to present experimental results showing the threshold voltage (VTH) and gate leakage current (IGSS) behaviour of SiC MOSFETs when subjected to pulsed-gate switching bias and drain-source bias stress at high temperature over time. The results obtained are then used to investigate the gate-oxide reliability of SiC MOSFETs. 2D TCAD static simulation results showing electric field distribution near the SiC/SiO2 interface are also presented in this paper

Experimentally validated methodology for real-time temperature cycle tracking in SiC power modules

© 2018 Elsevier Ltd The ability to monitor temperature variations during the actual operation of power modules is key to reliability investigations and the development of lifetime prediction strategies. This paper proposes an original solution, specifically devised with novel fast-switching silicon carbide (SiC) power MOSFETs in mind. The results show ability to track temperature variations resulting from active power cycling of the devices, including high speed transients, thus enabling to discriminate among different potential failure mechanisms. Validation of the proposed methodology and its accuracy is carried out with the support of infrared thermography