GaN device as one potential power electronics device has been gained much attention recently. One of the power conversion systems, ANPC inverter using GaN HEMT is potentially considered to be prospective usage of low loss and high efficiency. In this work, we demonstrate one optimised PWM scheme aims at balancing the device electro-thermal stress based on Parma PWM to control 3-Level ANPC GaN inverter. The method is to decrease the loss for switches account for the large loss and increase the loss for switches with less thermal stress initially. The simulation and experimental results prove the effectiveness of the optimised PWM in controlling the loss distribution

Castellazzi, Alberto

Gurpinar, Emre

Hussein, A.

Zeng, Y.

Name not available

Experimental demonstration of an optimised PWM scheme for more even device electro-thermal stress in a 3-Level ANPC GaN inverter

Nottingham eTheses

1 Experimental Demonstration of an Optimised PWM Scheme for More Even Device Electro-Thermal Stress in a 3-Level ANPC GaN Inverter Y Zeng*, E Gurpinar, A Hussein, Z Wang, A Castellazzi  *University of Nottingham, UK, eeyyqz@nottingham.ac.uk,     Keywords: GaN HEMT, Single Phase 3L ANPC Inverter, Optimised PWM control. Abstract GaN device as one potential power electronics device has been gained much attention recently. One of the power conversion systems, ANPC inverter using GaN HEMT is potentially considered to be prospective usage of low loss and high efficiency. In this work, we demonstrate one optimised PWM scheme aims at balancing the device electro-thermal stress based on Parma PWM to control 3-Level ANPC GaN inverter. The method is to decrease the loss for switches account for the large loss and increase the loss for switches with less thermal stress initially. The simulation and experimental results prove the effectiveness of the optimised PWM in controlling the loss distribution.  1 Introduction Although the applications of GaN HEMT are still in their infancy, in recent years, the GaN HEMT has emerged as a promising device for high frequency, high efficiency, high density power conversion due to a better figure of merit than comparable Si and SiC transistors. [1] The review of recent progresses in the development of wide band gap power semiconductor devices and the introduction of their basic applications such as Sic and GaN rectifiers are summarized in [2] in 2015.   In the past century, plenty of topologies of DC/AC inverters have been created to comply with different application requirement. [3] One class of the topologies, half-bridge topologies, are popular due to natural rejection of high-frequency common mode voltage variation at the output of the inverter that causes high leakage current injection to grid. Half-bridge topologies require double voltage input in comparison to full-bridge topologies, nevertheless various topologies show that they can maintain competitive efficiency with minimum number of components. [4]   The Active Neutral Point Clamped (ANPC) inverter is a member of half-bridge neutral point clamped inverter family, introduced in [5], [6] as an alternative to neutral point clamped (NPC) inverter for improved loss balancing and better utilization of semiconductor chip areas in the inverter. [7] A new attempt of a fully GaN HEMT based ANPC inverter, which aims to explore the benefits of the use of such device technology on the system level efficiency, power density and reliability was presented by Emre in [8] using normally-off p-gate GaN HEMTs by Panasonic. One of the modulation strategy based on reverse conduction capabilityfor GaN HEMT and SiC devices in [9], employing parallel conduction of the devices during the freewheeling phases of the output current in order to pursue high power efficiency. However, the obvious limitation that the imbalanced loss distribution among each switch decreases the lifetime and the reliability of the system.  In this paper, the new optimised PWM are presented in order for more even device electro-thermal stress among six switches in 3-Level single phase ANPC inverter. Section 2 introduces the theories of new optimised PWM and their loss calculation. Section 3 shows the simulation and experimental results and discussion for the new modulation scheme and followed by a possible improvement in section 4. 2 ANPC inverter and two PWM schemes 2.1 ANPC inverter topology and comparison of two PWMs Figure 1(a) and (b) shows the ANPC topology and the original PWM. Table 1 summarizes the switching states for 3L ANPC inverter. The positive voltage is applied to the output of by turning-on S1 and S3 and the output current flows through the two devices in series. During the positive active-state, S4 ensures an equal DC-link voltage sharing between S5 and S6 without conducting any current. The transition from positive active-state to zero-state is accomplished by switching S1 off, and then simultaneously switching S2 and S5 on, and thus the current is divided in two parallel paths: S2-S3 and S4-S5. Same commutation scheme is used for complementary switches during the negative active state and the zero-state. This modulation method ensures low conduction losses at zero-states, and the outer switches (S1 and S6) are exposed to switching losses at unity power factor. Hence, the synchronous rectification capability of the transistors is utilized during zero state conduction. [7]  It is obvious that S2 only works in zero (0P, 0N and 0PN) states which will account for the minimum power loss. S1 and S3 have larger power loss due to positive-active (+VDC) switching 2 states. The same condition also happens in lower side. Therefore, the optimised PWM is designed to decrease the loss  (a) [9]                                           (b) [9] Figure 1: (a) Schematic of 3L ANPC inverter and (b) Parma PWM   Table 1 Switching states    Figure 2. Optimised PWM for 3L ANPC inverter  for S1 and S3 but increase the loss for S2 (same for the lower side). On one side, optimised signal introduces an extra dead time without affecting the commutation between zero and active states, but increase the number of switch in zero states for S2 and S4. On the other side, a time length which is the same as the dead time is substracted from the total conducting time for S1 and S3 every time when they are on, hence the conduction loss for S1 and S3 will decrease. The efficiency of two PWM schemes are expected to be the same. 2.2 Loss calculation Conduction loss analysis for each switch for PWM shown in Figure 1(b) were presented in [10]. The similar conduction loss calculation for optimised PWM control is summarized in Table 2: Table 2 Conduction loss for upper side devices    𝑃𝑐𝑜𝑛𝑑_𝑎 and 𝑃𝑐𝑜𝑛𝑑_𝑧 are the conductive loss for active and zero states respectively. 𝑃𝑑𝑡_𝑟𝑒𝑑 is the reduction in conduction loss. 𝑃𝑑𝑡1_𝑏𝑝 corresponds to dead-time conduction loss when the gate-source voltage is below threshold and 𝑃𝑑𝑡1_𝑢𝑝 corresponds to dead-time conduction loss when the device is turned on. 𝑃𝑑𝑡2_𝑏𝑝  corresponds to reverse conduction dead-time losses at the positive half of the output when the device is turned-off, and 𝑃𝑑𝑡2_𝑢𝑝  corresponds to increased conduction time at the negative half of the output voltage. [10] For the switching loss, assume the switching energy is constant and the switching loss is 𝑃𝑠𝑤 = 𝐸𝑠𝑤𝑓. For unipolar PWM used in this experiment, the number of switching angle 𝑛 =𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 𝑓𝑚𝑜𝑑𝑢𝑙𝑎𝑡𝑖𝑛𝑔⁄ . Therefore, the switching loss for upper side switched are summarized in Table 3. Table 3 Switching loss for upper side devices    Due to symmetry and simplification, the lower side loss is the same as the upper side. Therefore, the total loss is 𝑃𝑙𝑜𝑠𝑠 = 𝑃𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 + 𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 where  𝑃𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 = 2(𝑃𝑐𝑜𝑛𝑑𝑆1 + 𝑃𝑐𝑜𝑛𝑑𝑆2 + 𝑃𝑐𝑜𝑛𝑑𝑆3) and  𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 = 2(𝑃𝑠𝑤1 + 𝑃𝑠𝑤2 + 𝑃𝑠𝑤3) . 3 Results and discussions 3.1 Simulation results The plecs was used to simulate 3L ANPC inverter with two different PWM schemes. The device was chosen as normally off p-gate GaN HEMT with the output characteristics shown in figure 5, followed by table 5 shows the simulation parameters. Thermal model in plecs was constructed using figure 3.  Figure 3 output characteristics of GaN device used [10] Table 5 simulation parameters  3 The typical loss distribution for two PWM are shown in Figure 4.                                             Figure 4 (a)   Figure 4 (b) Figure 4:  Power loss distribution for each device when input power is 400V, output power is 1KW. (a) Optimised PWM (b) Parma PWM  From Figure 4 (a), the optimised point for balanced loss distribution is when input voltage is 400V, output power is 1KW and carrier frequency is 16KHz. Therefore, optimised PWM prefers low frequency and low power. 3.2 Experimental settings The ANPC inverter used was designed by Emre and the introduction of the device can be found in [10]. The top view of the inverter is shown in Figure 5   Figure 5 Top view of the ANPC inverter prototype [10] It embeds the fiber optic receivers for transfer of PWM signals from an FPGA board, individual isolated gate drivers for each switch, film decoupling capacitors and a temperature controlled thermal management device, consisting of two cooling fans and two heating resistors mounted at the sides of a heat-sink to decouple the parametric temperature study from load conditions and switching frequency. [10]  The gate driver design still uses hard switching but the switching loss could be less compared with conventional squared pulse. The design method and pulse construction shown in Figure 6.  Figure 6 (a) [10]  Figure 6 (b) [10] Figure 6: (a) Schematic of GaN HEMT gate driver (b) Gate driver pulse Figure 7(b) shows the experimental settings, the connection was based on figure 7(a).  Figure 7(a) [10]  Figure 7(b) Figure 7: (a) Schematic of test connection (b) Photo of experiment settings 3.3 Experiment results The experiment was done when input voltage was 200V and output voltage was 250W. In order to find loss distribution of each device, we measured the case temperature of each device by thermocouple because the temparature is proportional to the loss. To avoid the bulk heatsink balancing the loss distribution automaticlly, we used individual small heatsink 0123456780 20 40 60 80 100 120 140 160 180Loss for each device vs carrier frequency using optimised PWMS1 S2 S3 S4 S5 S60123450 10 20 30 40 50 60 70Loss for each device vs carrier frequency using Parma PWMS1 S2 S3 S4 S5 S64 with fans. The initial tempareture for each device should be almost the same. (the difference should less than 1 degree). The real-time temperature waveform could be seen on Picolog recorder. After all the devices reached the steady state, the steady state tempratures were recorded. The steps were the same for both original Parma PWM and the optimised one. The temparature data were summarised in Table 4 and Table 5.  Table 4 Temprature records for Parma PWM     Table 5 Temparature records for Optimised PWM      Figure 7 The output current after filtering and output current before filtering   Figure 8 The comparision of steady state temprature between two PWM control schemes   Figure 7 shows the output waveforms of current and voltage, the current and voltage was measured before replacing the bulk heatsink by inidividual heatsinks. The input was 400V and output power was 1KW. From Figure 8, the loss for S2 and S4  increase whilst the loss for S3 and S5 decrease. The loss distribution using optimised PWM is more banlanced  than original PWM. Furthermore, the efficiency measured by power analyzer shown that the efficiency for parma and optimised PWM are 99.071% and 99.054% respectively.  4 Conclusion and future work The loss control and generalization of inverter will be much easier if the balanced loss distribution could be achieved. Parma PWM was designed to achieve high efficiency and the Parma PWM based optimised PWM aims to balance the power loss as well as maintaining high efficiency are proved to be effective experimentally.   The switching loss was increased by adding more number of switching times for switches which only work in zero states, and the conduction loss was decreased by one dead time interval for every conducting time for the switches work in both active and zero states. The simulation results show that the most optimised point to achieve the same loss distribution is when input voltage is 400V, output power is 1KW and carrier frequency is 16KHz. The power loss is around 2W for each switch.   The experiment was done only in low input and low output condition because the use of small individual cooling systems which could not withstand high output power. High temperature will damage the device. Therefore, a newly designed individual cooling system is under experimenting which can solve the problem in the future.   References [1]  X. Huang, Q. Li, Z. Liu and F. Lee, "Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration", IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2208-2219, 2014. [2] J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas and J. Rebollo, "A Survey of Wide Bandgap Power Semiconductor Devices", IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2155-2163, 2014. [3] Luo, F., & Ye, H. (2013). Advanced DC/AC inverters : Applications in renewable energy / Fang Lin Luo, Hong Ye. (Power electronics, electrical engineering, energy, and nanotechnology series ; 1). Boca Raton, Fla. ; London. [4] D. Barater, C. Concari, G. Buticchi, E. Gurpinar, D. De and A. Castellazzi, "Performance Evaluation of a Three-Level ANPC Photovoltaic Grid-Connected Inverter With 650-V SiC Devices and Optimized PWM", IEEE Transactions on Industry Applications, vol. 52, no. 3, pp. 2475-2485, 2016. 5 [5] T. Bruckner and S. Bemet, “Loss balancing in three-level voltage source inverters applying active NPC switches,” in 2001 IEEE 32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230), vol. 2. IEEE, 2001, pp. 1135–1140. [6] T. Bruckner, S. Bernet and H. Guldner, "The Active NPC Converter and Its Loss-Balancing Control", IEEE Transactions on Industrial Electronics, vol. 52, no. 3, pp. 855-868, 2005. [7] E. Gurpinar and A. Castellazzi, "600 V normally-off p-gate GaN HEMT based 3-level inverter," 2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017 - ECCE Asia), Kaohsiung, 2017, pp. 621-626. [8] E. Gurpinar, A. Castellazzi, F. Iannuzzo, Y. Yang and F. Blaabjerg, "Ultra-low inductance design for a GaN HEMT based 3L-ANPC inverter," 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1-8. [9] E. Gurpinar, D. De, A. Castellazzi, D. Barater, G. Buticchi and G. Francheschini, "Performance analysis of SiC MOSFET based 3-level ANPC grid-connected inverter with novel modulation scheme," 2014 IEEE 15th Workshop on Control and Modeling for Power Electronics (COMPEL), Santander, 2014, pp. 1-7. [10] E. Gurpinar and A. Castellazzi, "Trade-off Study of Heat Sink and Output Filter Volume in a GaN HEMT Based Single Phase Inverter", IEEE Transactions on Power Electronics, pp. 1-1, 2017.    

Nottingham ePrints

Zeng, Y. and Gurpinar, Emre and Hussein, A. and Castellazzi, Alberto (2018) Experimental Demonstration of an Optimised PWM Scheme for More Even Device Electro-Thermal Stress in a 3-Level ANPC GaN Inverter. In: 9th International Conference on Power Electronics, Machines and Drives (PEMD 2018), 17-19 April 2018, Liverpool, UK. Access from the University of Nottingham repository: http://eprints.nottingham.ac.uk/51445/1/Experimental%20Demonstration%20of%20an%20Optimised%20PWM%20Scheme%20for%20More%20Even%20Device%20Electro-Thermal%20Stress%20in%20a%203-Level%20ANPC%20GaN%20Inverter.pdfCopyright and reuse: The Nottingham ePrints service makes this work by researchers of the University of Nottingham available open access under the following conditions.This article is made available under the University of Nottingham End User licence and may be reused according to the conditions of the licence.  For more details see: http://eprints.nottingham.ac.uk/end_user_agreement.pdfA note on versions: The version presented here may differ from the published version or from the version of record. If you wish to cite this item you are advised to consult the publisher’s version. Please see the repository url above for details on accessing the published version and note that access may require a subscription.For more information, please contact eprints@nottingham.ac.uk1 Experimental Demonstration of an Optimised PWM Scheme for More Even Device Electro-Thermal Stress in a 3-Level ANPC GaN Inverter Y Zeng*, E Gurpinar, A Hussein, Z Wang, A Castellazzi  *University of Nottingham, UK, eeyyqz@nottingham.ac.uk,     Keywords: GaN HEMT, Single Phase 3L ANPC Inverter, Optimised PWM control. Abstract GaN device as one potential power electronics device has been gained much attention recently. One of the power conversion systems, ANPC inverter using GaN HEMT is potentially considered to be prospective usage of low loss and high efficiency. In this work, we demonstrate one optimised PWM scheme aims at balancing the device electro-thermal stress based on Parma PWM to control 3-Level ANPC GaN inverter. The method is to decrease the loss for switches account for the large loss and increase the loss for switches with less thermal stress initially. The simulation and experimental results prove the effectiveness of the optimised PWM in controlling the loss distribution.  1 Introduction Although the applications of GaN HEMT are still in their infancy, in recent years, the GaN HEMT has emerged as a promising device for high frequency, high efficiency, high density power conversion due to a better figure of merit than comparable Si and SiC transistors. [1] The review of recent progresses in the development of wide band gap power semiconductor devices and the introduction of their basic applications such as Sic and GaN rectifiers are summarized in [2] in 2015.   In the past century, plenty of topologies of DC/AC inverters have been created to comply with different application requirement. [3] One class of the topologies, half-bridge topologies, are popular due to natural rejection of high-frequency common mode voltage variation at the output of the inverter that causes high leakage current injection to grid. Half-bridge topologies require double voltage input in comparison to full-bridge topologies, nevertheless various topologies show that they can maintain competitive efficiency with minimum number of components. [4]   The Active Neutral Point Clamped (ANPC) inverter is a member of half-bridge neutral point clamped inverter family, introduced in [5], [6] as an alternative to neutral point clamped (NPC) inverter for improved loss balancing and better utilization of semiconductor chip areas in the inverter. [7] A new attempt of a fully GaN HEMT based ANPC inverter, which aims to explore the benefits of the use of such device technology on the system level efficiency, power density and reliability was presented by Emre in [8] using normally-off p-gate GaN HEMTs by Panasonic. One of the modulation strategy based on reverse conduction capabilityfor GaN HEMT and SiC devices in [9], employing parallel conduction of the devices during the freewheeling phases of the output current in order to pursue high power efficiency. However, the obvious limitation that the imbalanced loss distribution among each switch decreases the lifetime and the reliability of the system.  In this paper, the new optimised PWM are presented in order for more even device electro-thermal stress among six switches in 3-Level single phase ANPC inverter. Section 2 introduces the theories of new optimised PWM and their loss calculation. Section 3 shows the simulation and experimental results and discussion for the new modulation scheme and followed by a possible improvement in section 4. 2 ANPC inverter and two PWM schemes 2.1 ANPC inverter topology and comparison of two PWMs Figure 1(a) and (b) shows the ANPC topology and the original PWM. Table 1 summarizes the switching states for 3L ANPC inverter. The positive voltage is applied to the output of by turning-on S1 and S3 and the output current flows through the two devices in series. During the positive active-state, S4 ensures an equal DC-link voltage sharing between S5 and S6 without conducting any current. The transition from positive active-state to zero-state is accomplished by switching S1 off, and then simultaneously switching S2 and S5 on, and thus the current is divided in two parallel paths: S2-S3 and S4-S5. Same commutation scheme is used for complementary switches during the negative active state and the zero-state. This modulation method ensures low conduction losses at zero-states, and the outer switches (S1 and S6) are exposed to switching losses at unity power factor. Hence, the synchronous rectification capability of the transistors is utilized during zero state conduction. [7]  It is obvious that S2 only works in zero (0P, 0N and 0PN) states which will account for the minimum power loss. S1 and S3 have larger power loss due to positive-active (+VDC) switching 2 states. The same condition also happens in lower side. Therefore, the optimised PWM is designed to decrease the loss  (a) [9]                                           (b) [9] Figure 1: (a) Schematic of 3L ANPC inverter and (b) Parma PWM   Table 1 Switching states    Figure 2. Optimised PWM for 3L ANPC inverter  for S1 and S3 but increase the loss for S2 (same for the lower side). On one side, optimised signal introduces an extra dead time without affecting the commutation between zero and active states, but increase the number of switch in zero states for S2 and S4. On the other side, a time length which is the same as the dead time is substracted from the total conducting time for S1 and S3 every time when they are on, hence the conduction loss for S1 and S3 will decrease. The efficiency of two PWM schemes are expected to be the same. 2.2 Loss calculation Conduction loss analysis for each switch for PWM shown in Figure 1(b) were presented in [10]. The similar conduction loss calculation for optimised PWM control is summarized in Table 2: Table 2 Conduction loss for upper side devices    𝑃𝑐𝑜𝑛𝑑_𝑎 and 𝑃𝑐𝑜𝑛𝑑_𝑧 are the conductive loss for active and zero states respectively. 𝑃𝑑𝑡_𝑟𝑒𝑑 is the reduction in conduction loss. 𝑃𝑑𝑡1_𝑏𝑝 corresponds to dead-time conduction loss when the gate-source voltage is below threshold and 𝑃𝑑𝑡1_𝑢𝑝 corresponds to dead-time conduction loss when the device is turned on. 𝑃𝑑𝑡2_𝑏𝑝  corresponds to reverse conduction dead-time losses at the positive half of the output when the device is turned-off, and 𝑃𝑑𝑡2_𝑢𝑝  corresponds to increased conduction time at the negative half of the output voltage. [10] For the switching loss, assume the switching energy is constant and the switching loss is 𝑃𝑠𝑤 = 𝐸𝑠𝑤𝑓. For unipolar PWM used in this experiment, the number of switching angle 𝑛 =𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 𝑓𝑚𝑜𝑑𝑢𝑙𝑎𝑡𝑖𝑛𝑔⁄ . Therefore, the switching loss for upper side switched are summarized in Table 3. Table 3 Switching loss for upper side devices    Due to symmetry and simplification, the lower side loss is the same as the upper side. Therefore, the total loss is 𝑃𝑙𝑜𝑠𝑠 = 𝑃𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 + 𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 where  𝑃𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 = 2(𝑃𝑐𝑜𝑛𝑑𝑆1 + 𝑃𝑐𝑜𝑛𝑑𝑆2 + 𝑃𝑐𝑜𝑛𝑑𝑆3) and  𝑃𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 = 2(𝑃𝑠𝑤1 + 𝑃𝑠𝑤2 + 𝑃𝑠𝑤3) . 3 Results and discussions 3.1 Simulation results The plecs was used to simulate 3L ANPC inverter with two different PWM schemes. The device was chosen as normally off p-gate GaN HEMT with the output characteristics shown in figure 5, followed by table 5 shows the simulation parameters. Thermal model in plecs was constructed using figure 3.  Figure 3 output characteristics of GaN device used [10] Table 5 simulation parameters  3 The typical loss distribution for two PWM are shown in Figure 4.                                             Figure 4 (a)   Figure 4 (b) Figure 4:  Power loss distribution for each device when input power is 400V, output power is 1KW. (a) Optimised PWM (b) Parma PWM  From Figure 4 (a), the optimised point for balanced loss distribution is when input voltage is 400V, output power is 1KW and carrier frequency is 16KHz. Therefore, optimised PWM prefers low frequency and low power. 3.2 Experimental settings The ANPC inverter used was designed by Emre and the introduction of the device can be found in [10]. The top view of the inverter is shown in Figure 5   Figure 5 Top view of the ANPC inverter prototype [10] It embeds the fiber optic receivers for transfer of PWM signals from an FPGA board, individual isolated gate drivers for each switch, film decoupling capacitors and a temperature controlled thermal management device, consisting of two cooling fans and two heating resistors mounted at the sides of a heat-sink to decouple the parametric temperature study from load conditions and switching frequency. [10]  The gate driver design still uses hard switching but the switching loss could be less compared with conventional squared pulse. The design method and pulse construction shown in Figure 6.  Figure 6 (a) [10]  Figure 6 (b) [10] Figure 6: (a) Schematic of GaN HEMT gate driver (b) Gate driver pulse Figure 7(b) shows the experimental settings, the connection was based on figure 7(a).  Figure 7(a) [10]  Figure 7(b) Figure 7: (a) Schematic of test connection (b) Photo of experiment settings 3.3 Experiment results The experiment was done when input voltage was 200V and output voltage was 250W. In order to find loss distribution of each device, we measured the case temperature of each device by thermocouple because the temparature is proportional to the loss. To avoid the bulk heatsink balancing the loss distribution automaticlly, we used individual small heatsink 0123456780 20 40 60 80 100 120 140 160 180Loss for each device vs carrier frequency using optimised PWMS1 S2 S3 S4 S5 S60123450 10 20 30 40 50 60 70Loss for each device vs carrier frequency using Parma PWMS1 S2 S3 S4 S5 S64 with fans. The initial tempareture for each device should be almost the same. (the difference should less than 1 degree). The real-time temperature waveform could be seen on Picolog recorder. After all the devices reached the steady state, the steady state tempratures were recorded. The steps were the same for both original Parma PWM and the optimised one. The temparature data were summarised in Table 4 and Table 5.  Table 4 Temprature records for Parma PWM     Table 5 Temparature records for Optimised PWM      Figure 7 The output current after filtering and output current before filtering   Figure 8 The comparision of steady state temprature between two PWM control schemes   Figure 7 shows the output waveforms of current and voltage, the current and voltage was measured before replacing the bulk heatsink by inidividual heatsinks. The input was 400V and output power was 1KW. From Figure 8, the loss for S2 and S4  increase whilst the loss for S3 and S5 decrease. The loss distribution using optimised PWM is more banlanced  than original PWM. Furthermore, the efficiency measured by power analyzer shown that the efficiency for parma and optimised PWM are 99.071% and 99.054% respectively.  4 Conclusion and future work The loss control and generalization of inverter will be much easier if the balanced loss distribution could be achieved. Parma PWM was designed to achieve high efficiency and the Parma PWM based optimised PWM aims to balance the power loss as well as maintaining high efficiency are proved to be effective experimentally.   The switching loss was increased by adding more number of switching times for switches which only work in zero states, and the conduction loss was decreased by one dead time interval for every conducting time for the switches work in both active and zero states. The simulation results show that the most optimised point to achieve the same loss distribution is when input voltage is 400V, output power is 1KW and carrier frequency is 16KHz. The power loss is around 2W for each switch.   The experiment was done only in low input and low output condition because the use of small individual cooling systems which could not withstand high output power. High temperature will damage the device. Therefore, a newly designed individual cooling system is under experimenting which can solve the problem in the future.   References [1]  X. Huang, Q. Li, Z. Liu and F. Lee, "Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration", IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2208-2219, 2014. [2] J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas and J. Rebollo, "A Survey of Wide Bandgap Power Semiconductor Devices", IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2155-2163, 2014. [3] Luo, F., & Ye, H. (2013). Advanced DC/AC inverters : Applications in renewable energy / Fang Lin Luo, Hong Ye. (Power electronics, electrical engineering, energy, and nanotechnology series ; 1). Boca Raton, Fla. ; London. [4] D. Barater, C. Concari, G. Buticchi, E. Gurpinar, D. De and A. Castellazzi, "Performance Evaluation of a Three-Level ANPC Photovoltaic Grid-Connected Inverter With 650-V SiC Devices and Optimized PWM", IEEE Transactions on Industry Applications, vol. 52, no. 3, pp. 2475-2485, 2016. 5 [5] T. Bruckner and S. Bemet, “Loss balancing in three-level voltage source inverters applying active NPC switches,” in 2001 IEEE 32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230), vol. 2. IEEE, 2001, pp. 1135–1140. [6] T. Bruckner, S. Bernet and H. Guldner, "The Active NPC Converter and Its Loss-Balancing Control", IEEE Transactions on Industrial Electronics, vol. 52, no. 3, pp. 855-868, 2005. [7] E. Gurpinar and A. Castellazzi, "600 V normally-off p-gate GaN HEMT based 3-level inverter," 2017 IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017 - ECCE Asia), Kaohsiung, 2017, pp. 621-626. [8] E. Gurpinar, A. Castellazzi, F. Iannuzzo, Y. Yang and F. Blaabjerg, "Ultra-low inductance design for a GaN HEMT based 3L-ANPC inverter," 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1-8. [9] E. Gurpinar, D. De, A. Castellazzi, D. Barater, G. Buticchi and G. Francheschini, "Performance analysis of SiC MOSFET based 3-level ANPC grid-connected inverter with novel modulation scheme," 2014 IEEE 15th Workshop on Control and Modeling for Power Electronics (COMPEL), Santander, 2014, pp. 1-7. [10] E. Gurpinar and A. Castellazzi, "Trade-off Study of Heat Sink and Output Filter Volume in a GaN HEMT Based Single Phase Inverter", IEEE Transactions on Power Electronics, pp. 1-1, 2017.    

http://eprints.nottingham.ac.uk/51445/1/Experimental%20Demonstration%20of%20an%20Optimised%20PWM%20Scheme%20for%20More%20Even%20Device%20Electro-Thermal%20Stress%20in%20a%203-Level%20ANPC%20GaN%20Inverter.pdf

Experimental demonstration of an optimised PWM scheme for more even device electro-thermal stress in a 3-Level ANPC GaN inverter

Abstract

Similar works

Full text

Available Versions

Name not available

Name not available

Nottingham eTheses

Nottingham ePrints