The Economic Impact of Closing the Boundaries: The Lower Minho Valley Cross-Border Region in Times of Covid-19

This is an Accepted Manuscript of an article published by Taylor & Francis in Journal of Borderlands Studies on 2022-02-18, available at: https://doi.org/10.1080/08865655.2022.2039266The COVID-19 crisis experienced since early 2020 has been the first time in decades that all the boundaries between European Union member-states have been systematically re-set. This paper examines the economic impact derived from re-establishing the boundary on a particular cross-border region located between Galicia (Spain) and Portugal. The paper begins by outlining the theoretical considerations on the interplay between borders and economy. After examining the case-study area and the decisions taken by the Spanish and Portuguese authorities in an attempt to control the spread of the virus in 2020, the article explains the methods used to obtain the results. Two sets of results are presented. Firstly, the direct consequences for cross-border economic activities are considered. Secondly, the fall in Gross Domestic Product is quantified for sectors and municipalities in the cross-border region, distinguishing between, on the one hand, the overall effect caused by the restrictions due to the lockdown situation and, on the other, the precise impact attributed to the re-establishment of the international boundary. This is a worthy addition to previous literature given that this paper details the specific economic effects caused by the COVID- 19 crisis in a cross-border region directly affected by the boundary closure.AECT Río Miño Deputación de PontevedraS

Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI

The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sar-gantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (contract PID2019- 107255GB-C21), by the Generalitat de Catalunya (contract 2017-SGR-1328), by the European Union within the framework of the ERDF of Catalonia 2014-2020 under the DRAC project [001-P-001723], and by Lenovo-BSC Contract-Framework (2020). The Spanish Ministry of Economy, Industry and Competitiveness has partially supported M. Doblas and V. Soria-Pardos through a FPU fellowship no. FPU20-04076 and FPU20-02132 respectively. G. Lopez-Paradis has been supported by the Generalitat de Catalunya through a FI fellowship 2021FI-B00994. S. Marco-Sola was supported by Juan de la Cierva fellowship grant IJC2020-045916-I funded by MCIN/AEI/10.13039/501100011033 and by “European Union NextGenerationEU/PRTR”, and M. Moretó through a Ramon y Cajal fellowship no. RYC-2016-21104.Peer ReviewedPostprint (author's final draft

Pd-catalysed amidation of 2,6-dihalopurine nucleosides. Replacement of iodine at 0 ºC

Pd-catalysed reactions of 2-Cl, 2-Br and 2-I derivatives of a 6-chloropurine nucleoside with benzamide have been compared, using Pd2dba3, Xantphos and Cs2CO3 in toluene, between 20 and 80 °C. The reactivity order was 2-I > 2-Br > 6-Cl ≫ 2-Cl. The 2-I substituent could be replaced even at 0 °C, under conditions disclosed here for the first time. On the other hand, the replacement of the chlorine atom at position 2 (2-Cl) required 110 °C

DVINO: A RISC-V vector processor implemented in 65nm technology

This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedArticle signat per 43 autors/es: Guillem Cabo∗, Gerard Candón∗, Xavier Carril∗, Max Doblas∗, Marc Domínguez∗, Alberto González∗, Cesar Hernández†, Víctor Jiménez∗, Vatistas Kostalampros∗, Rubén Langarita∗, Neiel Leyva†, Guillem López-Paradís∗, Jonnatan Mendoza∗, Francesco Minervini∗, Julian Pavón∗, Cristobal Ramírez∗, Narcís Rodas∗, Enrico Reggiani∗, Mario Rodríguez∗, Carlos Rojas∗, Abraham Ruiz∗, Víctor Soria∗, Alejandro Suanes‡, Iván Vargas∗, Roger Figueras∗, Pau Fontova∗, Joan Marimon∗, Víctor Montabes∗, Adrián Cristal∗, Carles Hernández∗, Ricardo Martínez‡, Miquel Moretó∗§, Francesc Moll∗§, Oscar Palomar∗§, Marco A. Ramírez†, Antonio Rubio§, Jordi Sacristán‡, Francesc Serra-Graells‡, Nehir Sonmez∗, Lluís Terés‡, Osman Unsal∗, Mateo Valero∗§, Luís Villa† // ∗Barcelona Supercomputing Center (BSC), Barcelona, Spain. Email: [email protected]; †Centro de Investigación en Computación, Instituto Politécnico Nacional (CIC-IPN), Mexico City, Mexico; ‡ Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: [email protected]; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: [email protected] (author's final draft

Design and Implementation of HyperRAM Controller IP

Aquesta tesi té com a objectiu dissenyar i implementar un controlador IP HyperRAM per introduir-lo dins d'un System on Chip (SoC) de 65 nanòmetres anomenat DRAC 65nm. L'acrònim DRAC prové del nom del projecte Europeu: "Designing RISC-V-based Accelerators for next-generation Computers", liderat pel Barcelona Supercomputing Center (BSC). Els processadors i acceleradors creats per DRAC estan basats en la tecnologia RISC-V, i podran ser utilitzats en tasques de seguretat, medicina personalitzada i navegació autònoma. Tornant a l'HyperRAM, aquest tipus de memòries són ideals per a SoCs amb memòria RAM limitada que proporcionen una solució escalable per ampliar operacions ràpides de lectura i escriptura. En el nostre cas, partirem d'un tape-out previ anomenat preDRAC, on la implementació es divideix en una part ASIC i una part FPGA. Dins de la part FPGA resideix un controlador per una DDR3 RAM i un controlador per una RAM d'arrencada. Ara, l'objectiu principal és prescindir del controlador DDR3 RAM, ja que no tenim ni l'àrea ni els recursos per desenvolupar un controlador DDR3 i incloure'l al disseny ASIC. AixÍ, amb el controlador HyperRAM, podrem realitzar un funcionament autónom del SoC.This thesis aims to design and implement an HyperRAM controller IP to introduce it inside a System on Chip (SoC) of 65 nanometers called DRAC 65nm. The acronym DRAC comes from the name of the European project "Designing RISC-V-based Accelerators for next-generation Computers", lead by the Barcelona Supercomputing Center (BSC). The processors and accelerators created by DRAC are based on RISC-V technology, and they will be used to accelerate security tasks, personalised medicine, and autonomous navigation. Going back to the HyperRAM, these types of memories are ideal for SoCs with limited RAM, providing a scalable solution for extending fast read and write operations. In our case, we will start from a previous tape-out called preDRAC, where the implementation is divided between an Application-Specific Integrated Circuit (ASIC) part and an Field Programmable Gate Array (FPGA) part. Inside the FPGA part resides a DDR3 RAM controller and a boot RAM controller. Now, the main objective is to dispense the DDR3 RAM controller because we have neither the area nor the resources to develop a DDR3 controller and include it in the ASIC design. Thus, with the HyperRAM controller, we will perform a standalone operation of the SoC.Esta tesis tiene como objetivo diseñar e implementar un controlador IP HyperRAM para introducirlo dentro de un System on Chip (SoC) de 65 nanómetros denominado DRAC 65nm. El acrónimo DRAC proviene del nombre del proyecto Europeo: ”Designing RISCV- based Accelerators for next-generation Computers”, liderado por el Barcelona Supercomputing Center (BSC). Los procesadores y aceleradores creados por DRAC están basados en la tecnología RISC-V, y podrán ser utilizados en tareas de seguridad, medicina personalizada, y navegación autónoma. Volviendo al HyperRAM, estos tipos de memorias son ideales para SoCs con RAM limitada, proporcionando una solución escalable para extender operaciones rápidas de lectura y escritura. En nuestro caso, partiremos de un tape-out anterior denominado preDRAC, donde la implementación se divide entre una parte ASIC y una parte FPGA. Dentro de la parte FPGA reside un controlador para una DDR3 RAM y un controlador para una RAM de arranque. Ahora, el objetivo principal es prescindir del controlador DDR3 RAM ya que no tenemos ni el área ni los recursos para desarrollar un controlador DDR3 e incluirlo en el diseño ASIC. Así, con el controlador HyperRAM, podremos realizar un funcionamiento autónomo del SoC

Design, implementation and evaluation of post-quantum cryptography accelerators in 22nm FDSOI technology

This thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, a key-encapsulation mechanism (KEM) belonging to public-key cryptographic schemes (PKC). This cryptosystem is selected as one of the best KEMs from the National Institute of Standards and Technology (NIST) contest. Regarding the SoC, it belongs to the DRAC project, led by the Barcelona Supercomputing Center (BSC). The objective of this project is to design and implement RISC-V processors together with accelerators to optimize applications dedicated to PQC security, personalized medicine, and autonomous navigation. As for the CRYSTALS-Kyber accelerator, it has been designed using High-Level Synthesis (HLS) description. However, two different HLS approaches had to be performed to cover FPGA and ASIC targets. For the first target (FPGA), performance results provide almost 150x of speed-up concerning specific software executions. For the second target (ASIC), the accelerator implementation achieves 1GHz in the typical corner using 22nm FD-SOI commercial technology libraries

Espacios y destinos turísticos en tiempos de globalización y crisis

2 volúmenesXII Coloquio de Geografía del Turismo, Ocio y Recreación de la Asociación de Geógrafos Españoles. Colmenarejo (Madrid), del 17 al 19 de junio de 2010.Este libro ha sido editado con la colaboración económica del Ministerio de Ciencia e Innovación (ref. CS02010-10416-E)