Gain-of-function human STAT1 mutations impair IL-17 immunity and underlie chronic mucocutaneous candidiasis

Chronic mucocutaneous candidiasis disease (CMCD) may be caused by autosomal dominant (AD) IL-17F deficiency or autosomal recessive (AR) IL-17RA deficiency. Here, using whole-exome sequencing, we identified heterozygous germline mutations in STAT1 in 47 patients from 20 kindreds with AD CMCD. Previously described heterozygous STAT1 mutant alleles are loss-of-function and cause AD predisposition to mycobacterial disease caused by impaired STAT1-dependent cellular responses to IFN-γ. Other loss-of-function STAT1 alleles cause AR predisposition to intracellular bacterial and viral diseases, caused by impaired STAT1-dependent responses to IFN-α/β, IFN-γ, IFN-λ, and IL-27. In contrast, the 12 AD CMCD-inducing STAT1 mutant alleles described here are gain-of-function and increase STAT1-dependent cellular responses to these cytokines, and to cytokines that predominantly activate STAT3, such as IL-6 and IL-21. All of these mutations affect the coiled-coil domain and impair the nuclear dephosphorylation of activated STAT1, accounting for their gain-of-function and dominance. Stronger cellular responses to the STAT1-dependent IL-17 inhibitors IFN-α/β, IFN-γ, and IL-27, and stronger STAT1 activation in response to the STAT3-dependent IL-17 inducers IL-6 and IL-21, hinder the development of T cells producing IL-17A, IL-17F, and IL-22. Gain-of-function STAT1 alleles therefore cause AD CMCD by impairing IL-17 immunity

Using CTL formulae as component abstraction in a design and verification flow

International audienceIn the context of component-based design, the verification of global properties (involving several components) is difficult to achieve, due to combinatorial explosion problem, while the verification of each component is easier to perform. Following the idea of [24], we propose to build an abstraction of a component already verified, starting from a subset of its specification described as CTL formulae. This abstraction replaces the concrete component and alleviates the state-space explosion problem for checking global properties expressed in ACTL

Conception incrémentale, vérification de composants matériels et méthode d'abstraction pour la vérification de systèmes intégrés sur puce

Cette thèse traite de la vérification formelle par model checking de systèmes intégrés sur puce. Nous proposons d'abord une méthode de conception incrémentale pour la vérification d'un composant matériel. Cette méthode est un cadre de conception par ajouts successifs de nouveaux comportements. Nous avons montré que cette méthode assure la non-régression d'un composant tout au long de sa conception. D'autre part, cette méthode permet aussi de faire évoluer la spécification d'un composant en prenant en compte les différentes fonctionnalités ajoutées au cours de la conception. Nous avons ensuite particularisé cette approche pour la conception et la vérification d'architectures pipelines. Cette méthode a été utilisée avec succès pour laconception de convertisseurs de protocole. La vérification par model-checking d'un système intégré sur puce se confronte au problème d'explosion combinatoire. Les techniques d'abstractions sont des méthodes efficaces pour alléger ce problème. Nous exposons un algorithme d'abstraction basé sur la spécification de chaque composant. Cet algorithme construit une structure de Kripke représentant un sous-ensemble des formules CTL tirées de la spécification. Cette construction se place dans un contexte de raffinement d'abstraction guidé par l'étude du contre-exemple produit par le model checker. Les premières expérimentations que nous avons réalisées montrent un gain considérable en temps de vérification et un accroissement conséquent de la taille du système vérifié. Ces résultats nous confortent sur l'intérêt de cette méthode d'abstraction.PARIS-BIUSJ-Thèses (751052125) / SudocPARIS-BIUSJ-Mathématiques rech (751052111) / SudocSudocFranceF

Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process

International audienceEmbedded systems are usually composed of several components and in practice, these components generally have been independently verified to ensure that they respect their specifications before being integrated into a larger system. Therefore, we would like to exploit the specification (i.e. verified CTL properties) of the components in the objective of verifying a global property of the system. A complete concrete system may not be directly verifiable due to the state explosion problem, thus abstraction and eventually refinement process are required. In this paper, we propose a technique to select properties in order to generate a good abstraction and reduce refinement iterations. We have conducted several preliminary experimentations which show that our approach is promising in comparison to other abstraction-refinement techniques implemented in VIS [1]

Increasing the Accuracy of SAT-based Debugging

Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. In particular, debugging based on Boolean Satisfiability (SAT) has been shown to be quite efficient. Given some error traces, the algorithm returns fault candidates. But using random error traces cannot ensure that a fault candidate is sufficient to explain all erroneous behavior. Our approach provides a more accurate diagnosis by iterating the generation of counterexamples and debugging. This increases the accuracy of the debugging result and yields more valuable counterexamples. As a consequence less time consuming manual iterations between verification and debugging are required – thus the debugging productivity increases

Quantifying Robustness by Symbolic Model checking

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Complementary formal approaches for dependability analysis

International audienceEvaluating the robustness of digital circuits with respect to soft errors has become an important part of the design flow for many applications. The identification of the most or less critical registers is often necessary, in order to reach the lowest overheads while achieving a given application-level robustness. The goal here is to identify those soft errors actually harmful for the system, not to compute the Soft Error Rate. In this context, we investigate new approaches based on formal techniques to improve design-time robustness evaluations at least for the most critical blocks in a circuit. Preliminary results are shown, focusing on the evaluation of self-healing (or self-repairing) capabilities