11 research outputs found
A metabolomic approach to quality determination and authentication of raw plant material in the fragrance field. Iris rhizomes: A case study
Get PDFOxygenated heterocyclic compounds to differentiate Citrus spp. essential oils through metabolomic strategies
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Key low temperature processes for a silicon-based 3D sequential integration
No full textInternational audienc
Key low temperature processes for a silicon-based 3D sequential integration
No full textInternational audienc
Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration
No full textInternational audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (<500°C) needed for 3D Sequential Integration (3DSI). f T =180GHz & f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p
Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration
No full textInternational audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (<500°C) needed for 3D Sequential Integration (3DSI). f T =180GHz & f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p
Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices
No full textInternational audienc
Specificities of linear Si QD arrays integration and characterization
No full textInternational audienceThe low temperature operation of quantum computing devices implies developing characterization protocols, from extensive statistical tests to targeted device screening at cryogenic temperature. This paper reviews major integration constraints arising in linear Si quantum dots arrays and their implication on both the device operation and electrical characterization
