Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology

A low quiescent current low dropout voltage regulator with self-compensation

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is self-attained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology

Tracking and Data Relay Satellite System configuration and tradeoff study. Volume 2: Delta 2914 launched TDRSS, Configuration 2. Part 2: Final Report, 22 August 1972 - 1 April 1973

Configuration data and design information for a Delta 2914 launched configuration with greatly enhanced telecommunication service over the Part I Delta 2914 configuration is contained. The overall system definition, operations and control, and telecommunication service system, including link budgets are discussed. A brief description of the user transceiver and ground station is presented. A final section includes a summary description of the TDR spacecraft and all the subsystems. The data presented are largely in tabular form

A Capacitor-Less Wide-Band Power Supply Rejection Low Drop-Out Voltage Regulator with Capacitance Multiplier

A Low Drop-Out (LDO) voltage regulator with both capacitor-less and high power supply rejection (PSR) bandwidth attributes is highly admired for an integrated power management system of mobile electronics. The capacitor-less feature is demanded for realizing more compact device. The high PSR bandwidth is essential for being used with high frequency switching regulators. These two attributes are of strong trade-off because usually a capacitor-less LDO requires Miller Compensation which greatly limits the PSR bandwidth. This thesis presents a LDO design with both capacitor-less and high PSR bandwidth attributes. The proposed LDO structure incorporates external compensation which is gifted for extended PSR bandwidth. A capacitance multiplier (CM) of high multiplication factor (≈ 100) is designed to externally compensate the LDO without an external off-chip capacitor. In the proposed LDO circuit, NMOS is used as the pass transistor for system stabilization. Triple-well NMOS and Zero-Vt NMOS are used as pass transistors in the two main LDO designs. The design with the triple-well NMOS pass transistor aims at higher PSR bandwidth with lower power consumption. The design with Zero-Vt NMOS pass transistor eliminates the necessity of a charge pump for driving the gate of a NMOS pass transistor. Implemented in IBM 0.18μm technology, the LDO with triple-well NMOS achieves -40dB PSR to 19MHz with 265μA current consumption. The LDO with Zero-Vt NMOS achieves -40dB PSR to 10MHz with 350μA current consumption. In thisdesign, the feasibility of using Zero-Vt NMOS as a LDO pass transistor is proved. Moreover, compared to traditional capacitor-less LDOs with PSR bandwidth around 10kHz and above 0dB PSR beyond 10MHz, the PSR bandwidth of the proposed LDO structure is greatly extended with significant PSR over 10MHz. This also proves the feasibility of applying external compensation strategy to a capacitor-less LDO and its great beneficial effect on the PSR of the LDO

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Tracking and data relay satellite system configuration and tradeoff study. Volume 3: TDRSS configuration and data summary, part 1

A reference handbook of configuration data and design information is presented. It treats the overall system definition, operations and control, and telecommunication service system including link budgets. A brief description of the user transceiver and ground station is presented. A final section includes a summary description of the TDR spacecraft and all the subsystems. The data presented are largely in tabular form for easy reference

Tracking and data relay satellite system configuration and tradeoff study. Volume 5: TDRS spacecraft design, part 1

A dual spin stabilized TDR spacecraft design is presented for low data rate (LDR) and medium data rate (MDR) user spacecraft telecommunication relay service. The relay satellite provides command and data return channels for unmanned users together with duplex voice and data communication channels for manned user spacecraft. TDRS/ground links are in the Ku band. Command links are provided at UHF for LDR users and S band for MDR users. Voice communication channels are provided at UHF/VHF for LDR users and at S band for MDR users. The spacecraft is designed for launch on the Delta 2914 with system deployment planned for 1978. This volume contains a description of the overall TDR spacecraft configuration, a detailed description of the spacecraft subsystems, a reliability analysis, and a product effectiveness plan

Design of a 2.4 Ghz BAW-Based CMOS Transmitter

In recent years, bulk acoustic wave resonators (BAW) in combination with RF circuits have shown a big potential in achieving the low-power consumption and miniaturization level required to address wireless sensor nodes (WSN) applications. A lot of work has been focused on the receiver side, by integrating BAW resonators with low noise amplifiers (LNA) and in frequency synthesis with the design of BAW-based local oscillators, most of them working at fixed frequency due to their limited tuning range. At the architectural level, this has forced the implementation of several single channel transceivers. This thesis aims at exploring the use of BAW resonators in the transmitter, proposing an architecture capable of taking full advantage of them. The main objective is to develop a transmitter for WSN multi-channel applications able to cover the whole 2.4 GHz ISM band and enable the compatibility with wide-spread standards like Bluetooth and Bluetooth Low Energy. Typical transmissions should thus range from low data rates (typically tens of kb/s) to medium data rates (1 Mb/s), with FSK and GFSK modulation schemes, should be centered on any of the channels provided by these standards and cover a maximum transmission range of some tens of meters. To achieve these targets and circumvent the limited tuning range of the BAW oscillator, an up-conversion transmitter using wide IF is used. The typical spurs problems related to this transmitter architecture are addressed by using a combined suppression based on SSB mixing and selective amplification. The latter is achieved by cointegration of a high efficiency power amplifier with BAW resonators, which allows performing spurs filtering while preserving the efficiency. In particular the selective amplifier is designed by including in the PA analysis the BAW resonator parameters, which allows integrating the BAW filter into the passive network loading the amplifier, participating in the drain voltage shaping. Finally, the frequency synthesis section uses a fractional division plus LC PLL filtering and further integer division to generate the IF signals and exploit the very-low BAW oscillator phase noise. The transmitter has been integrated in a 0.18 µm standard digital CMOS technology. It allows addressing the whole 80 MHz wide 2.4 GHz ISM band. The unmodulated RF frequency carrier demonstrates a very-low phase noise of –136 dBc/Hz at 1 MHz offset. The IF spurs are maintained lower than –48 dBc, satisfying the international regulations for output power up to 10 dBm without the use of any quadrature error compensation in the transmitter. This is achieved thanks to the rejection provided by the SSB mixer and the selective amplifier, which can reach drain efficiency of up to 24% with integrated inductances, including the insertion losses of the BAW filter. The transmitter consumes 35.3 mA at the maximum power of 5.4 dBm under 1.6 V (1.2 V for the PA), while transmitting a 1 Mb/s GFSK signal and complying with both Bluetooth and Bluetooth Low Energy relative and absolute spectrum requirements