Variability-aware design of CMOS nanopower reference circuits

Questo lavoro è inserito nell'ambito della progettazione di circuiti microelettronici analogici con l'uso di tecnologie scalate, per le quali ha sempre maggiore importanza il problema della sensibilità delle grandezze alle variazioni di processo. Viene affrontata la progettazione di generatori di quantità di riferimento molto precisi, basati sull’uso di dispositivi che sono disponibili anche in tecnologie CMOS standard e che sono “intrinsecamente” più robusti rispetto alle variazioni di processo. Questo ha permesso di ottenere una bassa sensibilità al processo insieme ad un consumo di potenza estremamente ridotto, con il principale svantaggio di una elevata occupazione di area. Tutti i risultati sono stati ottenuti in una tecnologia 0.18μm CMOS. In particolare, abbiamo progettato un riferimento di tensione, ottenendo una deviazione standard relativa della tensione di riferimento dello 0.18% e un consumo di potenza inferiore a 70 nW, sulla base di misure su un set di 20 campioni di un singolo batch. Sono anche disponibili risultati relativi alla variabilità inter batch, che mostrano una deviazione standard relativa cumulativa della tensione di riferimento dello 0.35%. Abbiamo quindi progettato un riferimento di corrente, ottenendo anche in questo caso una sensibilità al processo della corrente di riferimento dell’1.4% con un consumo di potenza inferiore a 300 nW (questi sono risultati sperimentali ottenuti dalle misure su 20 campioni di un singolo batch). I riferimenti di tensione e di corrente proposti sono stati quindi utilizzati per la progettazione di un oscillatore a rilassamento a bassa frequenza, che unisce una ridotta sensibilità al processo, inferiore al 2%, con un basso consumo di potenza, circa 300 nW, ottenuto sulla base di simulazioni circuitali. Infine, nella progettazione dei blocchi sopra menzionati, abbiamo applicato un metodo per la determinazione della stabilità dei punti di riposo, basato sull’uso dei CAD standard utilizzati per la progettazione microelettronica. Questo approccio ci ha permesso di determinare la stabilità dei punti di riposo desiderati, e ci ha anche permesso di stabilire che i circuiti di start up spesso non sono necessari

Hardware for Memristive Neuromorphic Systems with Reliable Programming and Online Learning

Alternative computing technologies are highly sought after due to limitations on transistor fabrication improvements. Fabricated memristive technology allows for a non-volatile analog memory for neuromorphic computing. In an integrated CMOS process, the synapse circuits designed for a spiking neuromorphic system can use memristors to regulate accumulation in the neuron circuits. Testing the fabricated memristive devices composed of hafnium oxide and developing a model to represent the key device characteristics lead to specific design choices in implementing the analog memory core of the synapse circuit. The circuits I designed for neuromorphic computing in this process take advantage of the unique capabilities of the memristive device to store a programmable analog memory reliably and efficiently. I designed the peripheral circuitry required including the circuits for programming the memristor and for online learning capabilities

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Minimum power design of RF front ends

This thesis describes an investigation into the design of RF front ends with minimum power dissipation. The central question is: "What are the fundamental limits for the power dissipation of telecommunication front ends, and what design procedures can be followed that approach these limits and, at the same time, result in practical circuits?" After a discussion of the state of the art in this area, the elementary operations of a front end are identified. For each of these elementary operations, the fundamental limits for the power dissipation are discussed, divided into technology imposed limits and physics imposed limits. A traditional DECT front end design is used to demonstrate the large difference between the fundamental limits and the power dissipation of existing circuits. To improve this situation, first the optimum distribution of specifications across individual subcircuits needs to be determined, such that the requirements for a specific system can be fulfilled. This is achieved through the introduction of formal transforms of the specifications of subcircuits, which correspond with transforms of the subcircuit itself. Using these transforms, the optimum distribution of gain, noise, linearity and power dissipation can be determined. As it turns out, this optimum distribution can even be represented by a simple, analytical expression. This expression predicts that the power dissipation of the DECT front end can be reduced by a factor of 2.7 through an optimum distribution of the specifications. Using these optimum specifications of the subcircuits, the boundaries for further power dissipation reduction can be determined. This is investigated at the system, circuit and technology level. These insights are used in the design of a 2.5GHz wireless local area network, implemented in an optimized technology ("Silicon on Anything"). The power dissipation of the complete receiver is 3.5mW, more than an order of magnitude below other wireless LAN receivers in recent publications. Finally, the combination of this minimum power design method with a platform based development strategy is discussed

Reconfigurable electronics based on metal-insulator transition:steep-slope switches and high frequency functions enabled by Vanadium Dioxide

The vast majority of disruptive innovations in science and technology has been originated from the discovery of a new material or the way its properties have been exploited to create novel devices and systems. New advanced nanomaterials will have a lasting impact over the next decades, providing breakthroughs in all scientific domains addressing the main challenges faced by the world today, including energy efficiency, sustainability, climate and health. The electronics industry relied over the last decades on the miniaturization process based on the scaling laws of complementary metal-oxide semiconductors (CMOS). As this process is approaching fundamental limitations, new materials or physical principles must be exploited to replace or supplement CMOS technology. The aim of the work in this thesis is to propose the abrupt metal-insulator transition in functional oxides as a physical phenomenon enabling new classes of Beyond CMOS devices. In order to provide an experimental validation of the proposed designs, vanadium dioxide (VO2) has been selected among functional oxides exhibiting a metal-insulator transition, due to the possibility to operate at room temperature and the high contrast between the electrical properties of its two structural phases. A CMOS-compatible sputtering process for uniform large scale deposition of stoichiometric polycrystalline VO2 has been optimized, enabling high yield and low variability for the devices presented in the rest of the thesis. The high quality of the film has been confirmed by several electrical and structural characterization techniques. The first class of devices based on the MIT in VO2 presented in this work is the steep-slope electronic switch. A quantitative study of the slope of the electrically induced MIT (E-MIT) in 2-terminal VO2 switches is reported, including its dependence on temperature. Moreover, the switches present excellent ON-state conduction independently of temperature, suggesting MIT VO2 switches as promising candidates for steep-slope, highly conductive, temperature stable electronic switches. A novel design for the shape of the electrodes used in VO2 switches has been proposed, targeting a reduction in the actuation voltage necessary to induce the E-MIT. The electrothermal simulations addressing this effect have been validated by measurements. The potential of the MIT in VO2 for reconfigurable electronics in the microwave frequency range has been expressed by the design, fabrication and characterization of low-loss, highly reliable, broadband VO2 radio-frequency (RF) switches, novel VO2 tunable capacitors and RF tunable filters. The newly proposed tunable capacitors overcome the frequency limitations of conventional VO2 RF switches, enabling filters working at a higher frequency range than the current state-of-the-art. An alternative actuation method for the tunable capacitors has been proposed by integrating microheaters for local heating of the VO2 region, and the design tradeoffs have been discussed by coupled electrothermal and electromagnetic simulations. The last device presented in this work operates in the terahertz (THz) range; the MIT in VO2 has been exploited to demonstrate for the first time the operation of a modulated scatterer (MST) working at THz frequencies. The proposed MST is the first THz device whose working principle is based on the actuation of a single VO2 junction, in contrast to commonly employed VO2 metasurfaces

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-Force magnetometers

Tesi en modalitat de compendi de publicacionsToday, the most common form of mass-production semiconductor device fabrication is Complementary Metal-Oxide Semiconductor (CMOS) technology. The dedicated Integrated Circuit (IC) interfaces of commercial sensors are manufactured using this technology. The sensing elements are generally implemented using Micro-Electro-Mechanical-Systems (MEMS), which need to be manufactured using specialized micro-machining processes. Finally, the CMOS circuitry and the MEMS should ideally be combined in a single package. For some applications, integration of CMOS electronics and MEMS devices on a single chip (CMOS-MEMS) has the potential of reducing fabrication costs, size, parasitics and power consumption, compared to other integration approaches. Remarkably, a CMOS-MEMS device may be built with the back-end-of-line (BEOL) layers of the CMOS process. But, despite its advantages, this particular approach has proven to be very challenging given the current lack of commercial products in the market. The main objective of this Thesis is to prove that a high-performance MEMS, sealed and packaged in a standard package, may be accurately modeled and manufactured using the BEOL layers of a CMOS process in a reliable way. To attain this, the first highly reliable novel CMOS-MEMS Lorentz Force Magnetometer (LFM) was successfully designed, modeled, manufactured, characterized and subjected to several reliability tests, obtaining a comparable or superior performance to the typical solid-state magnetometers used in current smartphones. A novel technique to avoid magnetic offsets, the main drawback of LFMs, was presented and its performance confirmed experimentally. Initially, the issues encountered in the manufacturing process of MEMS using the BEOL layers of the CMOS process were discouraging. Vapor HF release of MEMS structures using the BEOL of CMOS wafers resulted in undesirable damaging effects that may lead to the conclusion that this manufacturing approach is not feasible. However, design techniques and workarounds for dealing with the observed issues were devised, tested and implemented in the design of the LFM presented in this Thesis, showing a clear path to successfully fabricate different MEMS devices using the BEOL.Hoy en día, la forma más común de producción en masa es una tecnología llamada Complementary Metal-Oxide Semiconductor (CMOS). La interfaz de los circuitos integrados (IC) de sensores comerciales se fabrica usando, precisamente, esta tecnología. Actualmente es común que los sensores se implementen usando Sistemas Micro-Electro-Mecánicos (MEMS), que necesitan ser fabricados usando procesos especiales de micro-mecanizado. En un último paso, la circuitería CMOS y el MEMS se combinan en un único elemento, llamado package. En algunas aplicaciones, la integración de la electrónica CMOS y los dispositivos MEMS en un único chip (CMOS-MEMS) alberga el potencial de reducir los costes de fabricación, el tamaño, los parásitos y el consumo, al compararla con otras formas de integración. Resulta notable que un dispositivo CMOS-MEMS pueda ser construido con las capas del back-end-of-line (BEOL) de un proceso CMOS. Pero, a pesar de sus ventajas, este enfoque ha demostrado ser un gran desafío como demuestra la falta de productos comerciales en el mercado. El objetivo principal de esta Tesis es probar que un MEMS de altas prestaciones, sellado y empaquetado en un encapsulado estándar, puede ser correctamente modelado y fabricado de una manera fiable usando las capas del BEOL de un proceso CMOS. Para probar esto mismo, el primer magnetómetro CMOS-MEMS de fuerza de Lorentz (LFM) fue exitosamente diseñado, modelado, fabricado, caracterizado y sometido a varias pruebas de fiabilidad, obteniendo un rendimiento comparable o superior al de los típicos magnetómetros de estado sólido, los cuales son usados en móviles actuales. Cabe destacar que en esta Tesis se presenta una novedosa técnica con la que se evitan offsets magnéticos, el mayor inconveniente de los magnetómetros de fuerza Lorentz. Su efectividad fue confirmada experimentalmente. En los inicios, los problemas asociados al proceso de fabricación de MEMS usando las capas BEOL de obleas CMOS resultaba desalentador. Liberar estructuras MEMS hechas con obleas CMOS con vapor de HF producía efectos no deseados que bien podrían llevar a la conclusión de que este enfoque de fabricación no es viable. Sin embargo, se idearon y probaron técnicas de diseño especiales y soluciones ad-hoc para contrarrestar estos efectos no deseados. Se implementaron en el diseño del magnetómetro de Lorentz presentado en esta Tesis, arrojando excelentes resultados, lo cual despeja el camino hacia la fabricación de diferentes dispositivos MEMS usando las capas BEOL.Postprint (published version

All-Silicon-Based Photonic Quantum Random Number Generators

Random numbers are fundamental elements in different fields of science and technology such as computer simulation like Monte Carlo-method simulation, statistical sampling, cryptography, games and gambling, and other areas where unpredictable results are necessary. Random number generators (RNG) are generally classified as “pseudo”-random number generators (PRNG) and "truly" random number generators (TRNG). Pseudo random numbers are generated by computer algorithms with a (random) seed and a specific formula. The random numbers produced in this way (with a small degree of unpredictability) are good enough for some applications such as computer simulation. However, for some other applications like cryptography they are not completely reliable. When the seed is revealed, the entire sequence of numbers can be produced. The periodicity is also an undesirable property of PRNGs that can be disregarded for most practical purposes if the sequence recurs after a very long period. However, the predictability still remains a tremendous disadvantage of this type of generators. Truly random numbers, on the other hand, can be generated through physical sources of randomness like flipping a coin. However, the approaches exploiting classical motion and classical physics to generate random numbers possess a deterministic nature that is transferred to the generated random numbers. The best solution is to benefit from the assets of indeterminacy and randomness in quantum physics. Based on the quantum theory, the properties of a particle cannot be determined with arbitrary precision until a measurement is carried out. The result of a measurement, therefore, remains unpredictable and random. Optical phenomena including photons as the quanta of light have various random, non-deterministic properties. These properties include the polarization of the photons, the exact number of photons impinging a detector and the photon arrival times. Such intrinsically random properties can be exploited to generate truly random numbers. Silicon (Si) is considered as an interesting material in integrated optics. Microelectronic chips made from Si are cheap and easy to mass-fabricate, and can be densely integrated. Si integrated optical chips, that can generate, modulate, process and detect light signals, exploit the benefits of Si while also being fully compatible with electronic. Since many electronic components can be integrated into a single chip, Si is an ideal candidate for the production of small, powerful devices. By complementary metal-oxide-semiconductor (CMOS) technology, the fabrication of compact and mass manufacturable devices with integrated components on the Si platform is achievable. In this thesis we aim to model, study and fabricate a compact photonic quantum random number generator (QRNG) on the Si platform that is able to generate high quality, "truly" random numbers. The proposed QRNG is based on a Si light source (LED) coupled with a Si single photon avalanche diode (SPAD) or an array of SPADs which is called Si photomultiplier (SiPM). Various implementations of QRNG have been developed reaching an ultimate geometry where both the source and the SPAD are integrated on the same chip and fabricated by the same process. This activity was performed within the project SiQuro—on Si chip quantum optics for quantum computing and secure communications—which aims to bring the quantum world into integrated photonics. By using the same successful paradigm of microelectronics—the study and design of very small electronic devices typically made from semiconductor materials—, the vision is to have low cost and mass manufacturable integrated quantum photonic circuits for a variety of different applications in quantum computing, measure, sensing, secure communications and services. The Si platform permits, in a natural way, the integration of quantum photonics with electronics. Two methodologies are presented to generate random numbers: one is based on photon counting measurements and another one is based on photon arrival time measurements. The latter is robust, masks all the drawbacks of afterpulsing, dead time and jitter of the Si SPAD and is effectively insensitive to ageing of the LED and to its emission drifts related to temperature variations. The raw data pass all the statistical tests in national institute of standards and technology (NIST) tests suite and TestU01 Alphabit battery without a post processing algorithm. The maximum demonstrated bit rate is 1.68 Mbps with the efficiency of 4-bits per detected photon. In order to realize a small, portable QRNG, we have produced a compact configuration consisting of a Si nanocrystals (Si-NCs) LED and a SiPM. All the statistical test in the NIST tests suite pass for the raw data with the maximum bit rate of 0.5 Mbps. We also prepared and studied a compact chip consisting of a Si-NCs LED and an array of detectors. An integrated chip, composed of Si p+/n junction working in avalanche region and a Si SPAD, was produced as well. High quality random numbers are produced through our robust methodology at the highest speed of 100 kcps. Integration of the source of entropy and the detector on a single chip is an efficient way to produce a compact RNG. A small RNG is an essential element to guarantee the security of our everyday life. It can be readily implemented into electronic devices for data encryption. The idea of "utmost security" would no longer be limited to particular organs owning sensitive information. It would be accessible to every one in everyday life