VHDL Implementation of High Performance and Dynamically Configured Multi-port Cache Memory

This project presents the implementation of 64x64 multi-port dynamically configured SRAM in VHDL (VHSIC hardware description language). It employs isolation nodes and dynamic memory partitioning algorithm to facilitate simultaneous multi-port accesses without duplicating bit-lines. VHDL test-bench is developed to verify the functionality of the dynamically configured memory. Results demonstrate that critical memory operations such as "read miss", "write miss" and "write bypass" can be performed using newly proposed low power, area efficient dynamically configured memory

Pendekodean Kanal Reed Solomon Berbasis FPGA untuk Transmisi Citra pada Sistem Komunikasi Satelit Nano

Sistem komunikasi satelit saat ini sedang dikembangkan oleh mahasiswa-mahasiswi ITS, salah satunya yaitu Sistem komunikasi satelit nano 2,4 GHz untuk pengiriman citra. Untuk mengatasi kerusakan informasi yang diterima akibat noise selama transmisi, maka di stasiun bumi dibutuhkan pendekodean kanal Reed Solomon (255,239) untuk mendeteki dan mengoreksi informasi jika terjadi kesalahan pada informasinya. Dalam makalah ini bertujuan untuk merancang pendekodean kanal Reed Solomon(255,239) untuk diimplementasikan pada stasiun bumi. Pendekodean ini secara teori mampu mendeteksi dan mengoreksi maksimum 8 simbol error yang terjadi pada informasi. Pendekodean Reed Solomon(255,239) dirancang menggunakan bahasa pemrograman VHDL (VHSIC Hardware Description Language) dan dimasukkan kedalam board FPGA (Field-Programmable Gate Array). Pengujiannya dilakukan hanya secara simulasi dengan menginjeksikan error pada data informasi yang diterima oleh Reed Solomon(255,239) karena relatif sulit diuji dengan menambahkan error saat tahap implementasi. Secara simulasi pendekodean ini telah mampu mengoreksi sebanyak 8 simbol error sesuai dengn teori. Pada tahap implementasinya juga telah berhasil karena telah mampu menerima informasi yang sesuai dengan informasi yang dikirim dengan asumsi tidak terdapat error pada informasi

Diseño de un elaborador VHDL

VHDL (VHSIC, Hardware Description Language) es un lenguaje de descripción hardware capaz de abarcar todo el ciclo de desarrollo de un sistema digital, desde los requisitos y necesidades iniciales hasta la simulación y validación del prototipo hardware de dicho sistema. Los lenguajes de descripción hardware se gestaron durante los años setenta, momento en el que se produjo un enorme desarrollo electrónico y tecnológico que provocó un cambio radical en los métodos de diseño de sistemas y de fabricación de sistemas digitales que existían en esa época

Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes

In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained

Purwarupa Mikroprosesor Berbasis Fpga Altera Epf10k10 dengan Deskripsi Vhdl

It has been designed and implemented an FPGA-based microprocessor prototype using Altera EPF10K10 and VHDL description then compiled and simulate using MAX+Plus II software. The microprocessor prototype is implementing using the Wizard A-01 development board and its assembly program stored in ROM. To decode and execute the instruction, it used Control Unit, which will send control signal to other components. The 16 instructions is implementing in this microprocessor prototype. This microprocessor prototype has 8-bit data bus and 4-bit address bus, implemented using 375 logic cells, operating at 14.72 MHz clock (maximum) and 3.68 MIPS

Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor

Towards remote monitoring and reconfiguration of FPGA-based controllers using IOPT-Tools

This work was partially financed by Portuguese Agency ”Fundac¸ao para a Ci ˜ encia e a Tecnologia” (FCT), in the ˆ framework of project UID/EEA/00066/2019.IOPT-Tools is a tool chain framework that supports controllers’ specification through Petri net models, models’ validation, and automatic generation of C and VHDL (VHSIC Hardware Description Language) code. Additionally, this framework supports the remote control and monitoring of embedded controllers that were implemented using the automatically generated C code. This paper presents an ongoing work where IOPT-Tools will be extended to support the remote control and monitoring of FPGA (Field Programmable Gate Array) based controllers. Additionally, the IOPT-Tools will be also extended to support the remote reconfiguration of FPGA-based controllers, enabling their adaptation to new application requirements.publishersversionpublishe

New approach for sensor simulation for Hardware In the Loop test systems

International audienceAutomatic test systems can evaluate the functionality of measurement and/or control hardware by simulating real world signals and verifying the expected response. Simulation takes the dynamics of real-world environments and models them using software to test the performance of critical system hardware components. Sensor simulation is the process of providing realistic sensor signals to the inputs of a device under test and evaluating how a piece of equipment will respond across a broad range of operating conditions. This paper will discuss the benefits of sensor simulation, and specifically reference the additional advantages to using an FPGA-based implementation

An Area-Optimized Chip of Ant Colony Algorithm Design in Hardware Platform Using the Address-Based Method

The ant colony algorithm is a nature-inspired algorithm highly used for solving many complex problems and finding optimal solutions; however, the algorithm has a major flaw and that is the vast amount of calculations and if the proper correction algorithm and architectural design are not provided, it will lead to the increasing use of hardware platform due to the high volume of operations; and perhaps at higher scales, it causes the chip area not to work because of the high number of problems; hence, the purpose of this paper is to save the hardware platform as far as possible and use it optimally through providing a particular algorithm running on a reconfigurable chip driven by the address-based method, so that the comparison of synthesis operations with the similar works shows significant improvements as much as 1/3 times greater than the other similar hardware methods.DOI:http://dx.doi.org/10.11591/ijece.v4i6.692

Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder

High-Efficiency Video Coding (HEVC) was developed to improve its predecessor standard, H264/AVC, by doubling its compression efficiency. As in previous standards, Motion Estimation (ME) is one of the encoder critical blocks to achieve significant compression gains. However, it demands an overwhelming complexity cost to accurately remove video temporal redundancy, especially when encoding very high-resolution video sequences. To reduce the overall video encoding time, we propose the implementation of the HEVC ME block in hardware. The proposed architecture is based on (a) a new memory scan order, and (b) a new adder tree structure, which supports asymmetric partitioning modes in a fast and efficient way. The proposed system has been designed in VHDL (VHSIC Hardware Description Language), synthesized and implemented by means of the Xilinx FPGA, Virtex-7 XC7VX550T-3FFG1158. Our design achieves encoding frame rates up to 116 and 30 fps at 2 and 4K video formats, respectively