Comparative analysis of analog LDO design

The presented research analyses different topologies of low dropout (LDO) regulator, mostly focusing on different frequency compensation schemes and power supply rejection analysis. This thesis discusses different analog LDO topologies and analyzes how they achieve stability using small signal analysis and related equations. The power supply rejection (PSR) of a different error amplifier and pass device has been analyzed and concluded that a Type-B amplifier with n-channel metal oxide semiconductor field effect transistor (MOSFET) output stage or a Type-A amplifier with p channel MOSFET (PMOS) output stage yields the best PSR. Digital LDO regulator topologies have also been discussed. The digital LDO regulator is intriguing due to its low power and synthesizability, but it suffers from coarse voltage regulation and poor PSR compared to the analog LDO regulator

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Power Supply Rejection Improvement Techniques In Low Drop-Out Voltage Regulators

Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA

Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications

Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (ΣΔ) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ΣΔ ADCs allow elimination of the anti‐aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ΣΔ ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high‐speed and low‐power applications. In addition, CT ΣΔ ADCs achieve high resolution due to the ΣΔ modulator’s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ΣΔ modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)–order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ΣΔ modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ΣΔ modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 μm CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 μA of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively

System-level design tool for switched capacitor DC-DC energy scavenging converters

This thesis deals with the system modelling and design of a Switched Capac- itor DC-DC (SC DC-DC) nano-power converter in Complementary Metal Oxide Semiconductor (CMOS) technology for energy harvesting applications. First of all, after a critical evaluation on the whole Integrated Circuit (IC) system structure, a Python script has been created in order to accurately analyse any system analytical behaviours before instantiating and running the Cadence usual simulations. The code is an upgrade with respect to a pre-existing one ([1]): several com- parisons are listed and explained to show the differences between the two, as well as stressing on our new dedicated features. In order to validate the model on the code, then, a feasibility study has been performed with a 180 nm United Microelectronics Corporation (UMC) technol- ogy process in the Cadence Virtuoso design suite. Good results let us state its reliability in being used both for the most of SC DC-DC architectures pre-design analysis and post-design verification: a full design space exploration shows how to use the script. Finally, the SC DC-DC circuit D for bluetooth applications that we present uses the Taiwan Semiconductor Manufacturing Company (TSMC) 55 nm technol- ogy process and its design has been mostly realized by Luca Intaschi, during his PhD, and Francesco Dalena from Dialog Semiconductor in Livorno. The circuit D converter is meant to be part of a sensor node (that needs to survive in total absence of battery recharge) supplied by a Thermo Electric Generator (TEG) which guarantees a very low input voltage to the system of about 0.2

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

An efficient frequency controlled PFM for DC-DC converters

As more features are being integrated into mobile platforms, the demand for long battery life during standby mode has been increasing. Light load efficiency becomes one of essential features in today's DC-DC converter. The most effective method to improve light load efficiency is to operate the DC-DC converter under pulse-frequency-modulation (PFM) to reduce the switching loss. However, using such architecture could also have the switching frequency get into the band of interest, and requires large off-chip components to filter unwanted signal. In this research, an efficient PFM with frequency limiting is designed. It has similar efficiency profile as the single pulse PFM by utilizing width switching and frequency control techniques. It operates in between 1~2 MHz switching frequency under light load condition

CMOS mobility-compensated time reference for crystal replacement

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2015.Apesar da existência de muitas alternativas para geração de base de tempo, não há ainda uma referencia de tempo totalmente integrável que possa oferecer simultaneamente alta precisão, baixa potência e custo de produção reduzido; portanto, não há uma referência de tempo ideal capaz de ter performance melhor do que os osciladores a quartzo disponíveis no mercado. O objetivo principal desse trabalho é de tentar encontrar uma solução em tecnologia CMOS de uma referencia de tempo capaz de substituir osciladores a quartzo na frequência de 32 kHz. Isso implica em projetar um oscilador de baixa potencia, alta precisão e que seja pouco sensível as variações de processo, de tensão e de temperatura. Os elementos básicos do oscilador de relaxação deste trabalho são um transistor zero-Vt que opera como resistor e uma fonte de corrente específica de transistor zero-Vt. Foi desenvolvido também um Schmitt trigger com entrada de corrente e uma fonte de corrente controlada por tensão capaz de acompanhar a variação de corrente devido as variações de processo, tensão e temperatura. As medidas do oscilador fabricados mostraram uma variação de +/- 30ppm/°C na faixa de temperatura de -20°C ate 80°C e uma variação menor do que +/- 500ppm/V para tensão de alimentação entre 0.7 V e 1.8 V. As medidas da estabilidade em frequência mostraram uma variação de +/- 500ppm para estabilidade de longo termo, e um jitter de 2 nano seconds para estabilidade curto termo.Abstract: Despite many alternatives for time generation, no CMOS fully-integrated time reference offers simultaneously high accuracy, low power consumption, and low cost, and, thus, no ideal time reference suitable to replace the xtalclockis available. The main aim of this work is to contribute to find a solution to this problem, which is to realize a low-cost, low-power CMOS time reference circuit that is insensitive to PVT (Process, Voltage, and Temperature) variations. The basic element of the relaxation oscillator is a zero-VtMOSFET that operates as a resistor and a current source which tracks the specific current of the zero-Vt transistor. The design presented here uses acurrent mode Schmitt trigger and a voltage controlled current source, which can track the current variation due to PVT variations. The frequency of oscillation, proportional to the mobility, is compensated by the thermal voltage. The proposed time reference, fabricated in a 180 nm CMOS technology has been designed for 32 kHz. Test and measurement results show a variation of +/- 30ppm/°C from -20°C to 80°C, and less than +/- 500ppm/V for a variation of the supply voltage between 0.7 V to 1.8 V. As regards frequency stability, measurements have shown a variation less than +/- 500ppm for long term stability, and an rms jitter of 2 nanoseconds (66 ppm) for short term stability

SIMPLIS efficiency model for a synchronous multiphase buck converter

In this master’s thesis, an efficiency model was developed for the synchronous multiphase buck converters of the TPS6594x-Q1 integrated circuit using SIMPLIS simulator. The model includes internal losses occurring in power stage transistors, power stage drivers and bondwires. Modeled external losses include printed circuit board resistance and inductance, inductor direct and alternating current characteristics as well as capacitor nonidealities. Internal loss modeling was mostly based on Cadence simulations. Power stage transistors especially were thoroughly modeled. The capacitances of the power stage transistors were extracted by integrating gate and drain currents during the transistor on and off transitions. Charging of the parasitic capacitances followed the theory in turn-off and turn-on transitions and therefore the capacitance extraction was fairly simple. Nonlinearities of the parasitic capacitors were modeled in SIMPLIS with multiple linear approximations. Transistor gate drivers were very rough approximations of the real drivers but good enough for the simulation model. Drivers were modeled to match the gate currents simulated in Cadence, which were then combined the accurate switching transistor models in order to accurately model the switching characteristics. External loss models were based on measurements and simulations. Printed circuit board losses were based on Ansys simulations in which the printed circuit board inductances and resistances were solved from the geometry of the printed circuit board. Inductors were modeled to match the datasheet impedance and resistance graphs and the model was verified against the measurements done in the laboratory. An automated measurement testbench was done for the inductor measurements using LabVIEW and the results were parsed using Matlab. A ladder topology with resistances and inductances was used in the final inductor model to model the frequency characteristics of the inductor. The effect of direct current on inductance was also investigated but the inductance reduction did not have any significant impact on efficiency. Other external components such as capacitors also cause some external losses and they were modeled based on the capacitor datasheets. The simulation model was compared against single- and two-phase efficiency measurements with multiple different input and output voltages which were chosen to match the most common use cases. Efficiency curves were drawn for each configuration using the implemented simulation model and over 300 different comparison points were compared in total. A post processing script that was launched after a simulation completes had to be written with the programming language SIMPLIS supports to draw the efficiency graph from the simulated data. Using the script allowed to run the efficiency simulation without any additional licenses other than the SIMPLIS license. The final model achieved an average error of under 1 % between all the measured and simulated efficiency curves. The most accurate results were obtained with lower switching frequency and larger inductance. Apart from accuracy, the simulator had to be practical and therefore the simulation time had to be considered. Simulation time was attempted to be kept at minimum by simplifying the schematic in as many ways as possible without losing accuracy. For example, reducing the point of the linear approximations in the power stage transistors from 79 points to 17 points saved nearly 50 seconds in single-phase simulations without significant changes in simulation accuracy