High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

This paper presents the design of 3.1-10.6 GHz class AB power amplifier (PA) suitable for medical body area network (MBAN) Ultra-Wide Band (UWB) applications in TSMC 0.18 µm technology. An optimization technique to simultaneously maximize power added efficiency(PAE) and minimize group delay variation is employed. Source and Load-pull contours are used to design inter and output stage matching circuits. The post-layout simulation results indicated that the designed PA has a maximum PAE of 32 % and an output 1-dB compression of 11 dBm at 4 GHz. In addition, a small group delay variation of ± 50 ps was realized over the whole required frequency band . Moreover, the proposed PA has small signal power gain (S21) of 12.5 dB with ripple less than 1.5 dB over the frequency range between 3.1 GHz to 10.6 GHz, while consuming 36 mW

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

Current reuse topology in UWB CMOS LNA

Non

Low Noise Amplifier using Darlington Pair At 90nm Technology

The demand of low noise amplifier (LNA) has been rising in today’s communication system. LNA is the basic building circuit of the receiver section satellite. The design concept demonstrates the design trade off with NF, gain, power consumption. This paper reports on with analysis of wideband LNA. This paper shows the schematic of LNA by using Darlington pair amplifier. This LNA has been fabricated on 90nm CMOS process. This paper is focused on to make comparison of three stage and single stage LNA. Here, the phase mismatch between these patameters is quantitavely analyzed to study the effect on gain and noise figure (NF). In this paper, single stage LNA has shown the 23 dB measured gain, while the three stages LNA has demonstrated 29 dB measured gain. Here, LNA designed using darlington pair shows low NF of 3.3-4.8 dB, which comparable to other reported single stage LNA designs and appreciably low compared to the three stages LNA. Hence, findings from this paper suggest the use of single stage LNA designed using Darlington pair in transceiver satellite applications

CMOS Power Amplifier Design Techniques for UWB Communication: A Review

This paper reviews CMOS power amplifier (PA) design techniques in favour of ultra-wideband (UWB) application. The PA circuit design is amongst the most difficult delegation in developing the UWB transmitter due to conditions that must be achieved, including high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. In order to meet these requirements, many researchers came up with different techniques. Among the techniques used are distributed amplifiers, resistive shunt feedback, RLC matching, shuntshunt feedback, inductive source degeneration, current reuse, shunt peaking, and stagger tuning. Therefore, problems and limitation of UWB CMOS PA and circuit topology are reviewed. A number of works on the UWB CMOS PA from the year 2004 to 2016 are reviewed in this paper. In recent developments, UWB CMOS PA are analysed, hence imparting a comparison of performance criteria based on several different topologies

Timed array antenna system : application to wideband and ultra-wideband beamforming receivers

Antenna array systems have a broad range of applications in radio frequency (RF) and ultra-wideband (UWB) communications to receive/transmit electromagnetic waves from/to the sky. They can enhance the amplitude of the input signals, steer beams electronically, and reject interferences thanks to beamforming technique. In an antenna array beamforming system, delay cells with the tunable capability of delay amount compensate the relative delay of signals received by antennas. In fact, each antenna almost acts individually depending upon time delaying effects on the input signals. As a result, the delay cells are the basic elements of the beamforming systems. For this purpose, novel active true time delay (TTD) cells suitable for RF antenna arrays have been presented in this thesis. These active delay cells are based on 1st- and 2nd-order all-pass filters (APFs) and achieve quite a flat gain and delay within up to 10-GHz frequency range. Various techniques such as phase linearity and delay tunability have been accomplished to improve the design and performance. The 1st-order APF has been designed for a frequency range of 5 GHz, showing desirable frequency responses and linearity which is comparable with the state-of-the-art. This 1st-order APF is able to convert into a 2nd-order APF via adding a grounded capacitor. A compact 2nd-order APF using an active inductor has been also designed and simulated for frequencies up to 10 GHz. The active inductor has been utilized to tune the amount of delay and to reduce the on-chip size of the filter. In order to validate the performance of the delay cells, two UWB four-channel timed array beamforming receivers realized by the active TTD cells have been proposed. Each antenna channel exploits digitally controllable gain and delay on the input signal and demonstrates desirable gain and delay resolutions. The beamforming receivers have been designed for different UWB applications depending on their operating frequency ranges (that is, 3-5 and 3.1-10.6 GHz), and thus they have different system requirements and specifications. All the circuits and topologies presented in this dissertation have been designed in standard 180-nm CMOS technologies, featuring a unity gain frequency ( ft) up to 60 GHz.Els sistemes matricials d’antenes tenen una àmplia gamma d’aplicacions en radiofreqüència (RF) i comunicacions de banda ultraampla (UWB) per rebre i transmetre ones electromagnètics. Poden millorar l’amplitud dels senyals d’entrada rebuts, dirigir els feixos electrònicament i rebutjar les interferències gràcies a la tècnica de formació de feixos (beamforming). En un sistema beamforming de matriu d’antenes, les cèl·lules de retard amb capacitat ajustable del retard, compensen aquest retard relatiu dels senyals rebuts per les diferents antenes. De fet, cada antena gairebé actua individualment depenent dels efectes de retard de temps sobre el senyals d’entrada. Com a resultat, les cel·les de retard són els elements bàsics en el disseny dels actuals sistemes beamforming. Amb aquest propòsit, en aquesta tesi es presenten noves cèl·lules actives de retard en temps real (TTD, true time delay) adequades per a matrius d’antenes de RF. Aquestes cèl·lules de retard actives es basen en cèl·lules de primer i segon ordre passa-tot (APF), i aconsegueixen un guany i un retard força plans, en el rang de freqüència de fins a 10 GHz. Diverses tècniques com ara la linealitat de fase i la sintonització del retard s’han aconseguit per millorar el disseny i el rendiment. La cèl·lula APF de primer ordre s’ha dissenyat per a un rang de freqüències de fins a 5 GHz, mostrant unes respostes freqüencials i linealitat que són comparables amb l’estat de l’art actual. Aquestes cèl·lules APF de primer ordre es poden convertir en un APF de segon ordre afegint un condensador més connectat a massa. També s’ha dissenyat un APF compacte de segon ordre que utilitza una emulació d’inductor actiu per a freqüències de treball de fins a 10 GHz. S’ha utilitzat l'inductor actiu per ajustar la quantitat de retard introduït i reduir les dimensions del filtre al xip. Per validar les prestacions de les cel·les de retard propostes, s’han proposat dos receptors beamforming basats en matrius d’antenes de 4 canals, realitzats por cèl·lules TTD actives. Cada canal d’antena aprofita el guany i el retard controlables digitalment aplicats al senyal d’entrada, i demostra resolucions de guany i retard desitjables. Els receptors beamforming s’han dissenyat per a diferents aplicacions UWB segons els seus rangs de freqüències de funcionament (en aquest cas, 3-5 i 3,1-10,6 GHz) i, per tant, tenen diferents requisits i especificacions de disseny del sistema. Tots els circuits i topologies presentats en aquesta tesi s’han dissenyat en tecnologies CMOS estàndards de 180 nm, amb una freqüència de guany unitari (ft) de fins a 60 GHz.Postprint (published version

A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications

In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for wideband applications. A common-gate input stage is used to improve the input impedance matching and linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure (NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply voltage of 0.8v