A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Abstract

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2