Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Journal of Telecommunications and Information Technology, 2004, nr 1

kwartalni

Advances in Amorphous Oxide Semiconductor Devices, Materials, and Processes for Customizable Scalable Manufacturing of Thin-Film Electronics

Electronic circuits comprised of thin-film transistors (TFTs) are essential to nearly every modern display technology. For decades, the TFT industry relied on amorphous silicon, but increasing performance demands required semiconductors with superior electron transport leading to the adoption of amorphous oxide semiconductors (AOS). The superior electron transport and ease of thin-film preparation of AOS has led to a growing interest in developing thin-film electronics for beyond-display technologies. These include monolithic 3D integration on Si complementary metal-oxide-semiconductor integrated circuits (ICs) – to continue Moore’s law, add new functionality, and improve performance – and flexible electronics for electronic skins, textiles, solar cells, and displays. In this thesis we facilitate the adoption of thin-film electronics for beyond-display technologies by: 1) developing uniform and conformal AOS deposition processes with record performance; 2) demonstrating expanded AOS capabilities by exploring new device architectures; and 3) developing a new additive manufacturing technique for customizable scalable manufacturing. First, we meet the performance and thermal budget requirements of AOS for beyond-display applications by using atomic-layer deposition (ALD) – a conformal, uniform, and precise vapor-phase deposition technique – and aggressively optimizing the process conditions. We discovered that improved electrical performance correlated with an increase in film density, which can be achieved by increasing deposition temperature, by post-deposition annealing, and by using plasma enhanced-ALD (PE-ALD). Second, we made innovations in device design to expand the range of circuit applications for AOS TFTs by exploiting the benefit of their wide-bandgap to fabricate high-voltage TFTs (HVTFTs). While the current handling capabilities of these HVTFTs cannot compete with conventional power electronics, the ability to deposit AOS materials directly on Si ICs may enable monolithic 3D integration of HVTFTs, adding new functionality as an HV interface to aggressively scaled low-voltage Si CMOS. Third, we show that ambient instabilities are caused by interactions between the surface of the AOS film and ambient molecules. We eliminate these instabilities by developing an ALD-based passivation layer. Fourth, we study the temporal and bias stress stability of our ALD AOS thin-film transistors and see excellent stability after the first month of aging and improved positive bias stress stability with passivation. Fifth, we investigate several materials to form a Schottky contact to ALD AOS films to enable future rectifier-based circuits and unipolar logic circuits. Finally, we develop an additive manufacturing approach for customizable manufacturing of AOS devices. Further improvement in device performance and reduction of channel length, enabled by the sub-µm precision of EHD, has the potential to yield fully customizable additive manufacturing of high-frequency circuits.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169721/1/allemang_1.pd

Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability

An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development

Design and performance analysis of Tri-gate GaN HEMTs

GaN-based high electron mobility transistors (HEMT) are promising devices for radio frequency (RF) and high-power electronics and are already in use for RF power amplifiers and for power switches. Commonly, these devices are normally-on transistors, i.e., they are in the on-state at zero applied gate voltage, what limits their suitability for various applications, such as fail-safe power switches and RF amplifiers with single-polarity power supply. Unfortunately, in contrast to GaAs- and InP HEMTs, achieving normally-off operation, i.e., a positive thresh-old voltage, for GaN heterostructures is difficult due to the high density of the polarization-induced two-dimensional electron gas (2DEG) at the barrier/buffer interface. For fast RF HEMTs, short gates are required. However, HEMTs with aggres-sively scaled gate length frequently suffer from short-channel effects caused by a degraded control of the gate over the channel. This leads to a deterioration of the transistors off-state performance (increased subthreshold swing and drain-induced barrier lowering) and on-state behavior (increased drain conductance). The tri-gate design has recently been applied to MOSFETs and HEMTs to improve the gate control and suppress short channel effects. Experimental tri-gate transistors show excellent down-scaling characteristics, improved performance, and, in particular for GaN tri-gate HEMTs, a significant shift of the threshold voltage toward positive values. On the other hand, tri-gate GaN normally-off HEMTs are still suffering from increased parasitics causing degraded RF performance (particularly in terms of cutoff frequency) compared to their planar counterparts. Improving the RF performance of GaN tri-gate HEMTs by reducing the parasitics is essential, but this requires a deep understanding of device physics and a thorough analysis of the root causes. In the present work, in-depth theoretical investigations of GaN tri-gate HEMT operation are performed and extensive simulation studies for these devices are conducted. As a result of these efforts, improved insights in the physics of GaN tri-gate HEMTs are achieved, the potential of this transistor type is assessed, design guidelines are elaborated, and advantageous designs are developed. It is shown that the 2DEG sheet density decreases by shrinking the body width, that the threshold voltage of GaN tri-gate HEMTs strongly depends on the width of AlGaN/GaN bodies, and that solely by decreasing the body width a transition from normally-on to normally-off operation can be achieved. The separation between adjacent bodies is shown to have less impact on threshold voltage. The results also show that for wide bodies (> 200 nm) the channel is controlled by both the top-gate and the sidewall gates, while for decreasing body width the control by top-gate gradually diminishes and the channel will be only controlled by side-gates. Furthermore, the impact of AlGaN barrier design (Al content, thickness) is studied, and the results show a limited dependency of the threshold voltage on the barrier design for very narrow bodies. The tri-gate concept enables normally-off operation, provides improved on-state performance (higher transconductance), and effectively suppresses short-channel effects in the off-state. Moreover, the simulation results show that GaN tri-gate HEMTs can exhibit higher breakdown voltages and operate closer to the theoretical limit for GaN devices than their planar counterparts. Moreover, the simulations indicate that the RF performance of GaN tri-gate HEMTs with optimized body designs can be superior to that of conventional planar devices. A means to improve the RF performance is the reduction of the body etch height, leading to a decreased parasitic coupling between the sidewalls and the source/drain electrodes. Thus, reducing the body height leads to a decreased overall gate capacitance and an improved RF performance. Another way to reduce the overall gate capacitance is to cover the body sidewalls with a dielectric (e.g. SiN). This reduces the fringing capacitance components since the gap between neighboring bodies that is filled with gate metal is narrower compared to the case without dielectrics. Finally, the polarization charge at the barrier/channel interface and thus the electron density in the 2DEG) can be increased either by increasing the aluminium content of the AlGaN barrier or by using a different barrier material (e.g., lattice matched In0.17 Al0.83 N). In the frame of a joint DFG project, GaN tri-gate HEMTs designed based on the improved insights in the physics of these devices have been fabricated and characterized at Fraunhofer IAF. These devices having a gate length of 100 nm are by far the fastest GaN tri-gate HEMTs worldwide and show record performance in terms of cutoff frequency (120 GHz) and maximum frequency of oscillation (300 GHz).HEMTs (high electron mobility transistors) auf GaN-Basis besitzen großes Potenzial für die HF- (Hochfrequenz) und Leistungselektronik und werden bereits in HF-Leistungsverstärkern und als Leistungsschalter verwendet. Üblicherweise sind GaN HEMTs Normally-On Transistoren (d.h. Transistoren, die sich bei einer Gatespannung von 0 V im Ein-Zustand befinden), was für Anwendungen wie Fail-Safe-Leistungsschalter und HF-Verstärker mit nur einer Versorgungsspannung nachteilig ist. Es schwierig, GaN HEMTs mit Normally-Off-Charakteristik (HEMTs mit positiver Schwellspannung) zu realisieren, da in diesen Transistoren die Dichte des sich an der Grenzfläche Barriere/Puffer ausbildenden 2DEG (zweidimensionales Elektronengas) auf Grund starker Polarisationseffekte erheblich größer als in GaAs und InP HEMTs ist. Die Realisierung schneller HF-HEMTs erfordert kurze Gates. Allerdings leiden Transistoren mit sehr kurzen Gates häufig unter Kurzkanaleffekten und einer reduzierten Steuerwirkung des Gates, was zu einer Verschlechterung des Verhaltens im Aus-Zustand (erhöhte Werte für den Subthreshold Swing und das Drain-Induced Barrier Low-ering) und im Ein-Zustand (erhöhter Drainleitwert) führt. In jüngster Zeit wird bei MOSFETs und HEMTs das Tri-Gate-Design angewendet, um die Gatesteuerwirkung zu verbessern und Kurzkanaleffekte zu unterdrücken. So wurden bereits Tri-Gate-Transistoren mit ausgezeichnetem Skalierungsverhalten, verbesserten Eigenschaften und, speziell im Fall von GaN Tri-Gate-HEMTs, positiver Schwellspannung, demonstriert. Auf der anderen Seite leiden GaN Tri-Gate-HEMTs mit Normally-Off-Charakteristik jedoch unter großen Parasitäten, die das HF-Verhalten (insbesondere die Transitfrequenz) beeinträchtigen. Die Verbesserung des HF-Verhaltens und eine Reduzierung der Parasitäten von GaN Tri-Gate-HEMTs ist daher dringend nötig. Das erfordert jedoch ein tiefes Eindringen in die Physik dieser Bauelemente. In der vorliegenden Arbeit werden umfassende theoretische Untersuchungen und Bauelementesimulationen zu GaN Tri-Gate-HEMT beschrieben, die zu einem deutlichen verbesserten Verständnis der Wirkungsweise von GaN Tri-Gate-HEMTs führten. So konnten das Potential dieses Transistortyps bewertet, Designregeln erarbeitet und vorteilhafte Transistordesigns entwickelt werden. In der Arbeit wird gezeigt, dass eine Verringerung der Bodyweite bei gegebener Gatespannung zu einer Verringerung der Ladungsträgerdichte im 2DEG führt, dass die Schwellspannung maßgeblich von der Bodyweite bestimmt wird und dass bei hinreichend geringer Bodyweite der Übergang vom Normall-On- zum Normally-Off-Betrieb erfolgt. Es wird auch gezeigt, dass der Abstand zwischen benachbarten Bodies nur einen geringen Einfluss auf die Schwellspannung hat. Darüber hinaus wird demonstriert, dass im Fall weiter Bodies (> 200 nm) der Kanal sowohl durch das Top-Gate als auch durch die Seiten-Gates gesteuert wird, während bei schmaleren Bodies die Steuerwirkung durch das Top-Gate geringer wird und die Verhältnisse im Kanal im Wesentlichen durch das Seiten-Gates bestimmt werden. In der Arbeit wird weiterhin Rolle des Designs der AlGaN-Barriere (Al-Gehalt, Dicke) untersucht und demonstriert, dass die Gestaltung der Barriere bei schmalen Bodies nur einen begrenzten Einfluss auf die Schwellspannung hat. Die Untersuchungen zeigen deutlich, dass das mit dem Tri-Gate-Konzept Normally-Off-Transistoren realisierbar sind, dass das Transistorverhalten im Ein-Zustand verbessert (höhere Steilheit) wird, und dass Kurzkanaleffekte im Aus-Zustand wirkungsvoll unterdrückt. Es wird auch demonstriert, dass GaN Tri-Gate HEMTs höhere Durchbruchspannungen zeigen und näher an der theoretischen Grenze für GaN-Bauelemente arbeiten als planare GaN HEMTs. Ein weiteres Ergebnis der vorliegenden Arbeit ist der Nachweis, dass GaN Tri-Gate-HEMTs mit sorgfältig optimiertem Design den planaren HEMTs auch hinsichtlich des HF-Verhaltens überlegen sind. Ein Mittel zur Verbesserung des HF-Verhaltens ist die Reduzierung der Body-Ätzhöhe, die zur Verringerung der parasitären Kopplung zwischen den Body-Seitenwänden und den Source/Drain-Elektroden und somit zu einer geringeren Gatekapazität führt. Eine weitere Maßnahme zur Reduzierung der Gatekapazität ist die Beschichtung der Body-Seitenwände mit einem Dielektrikum (z.B. SiN). Das verringert die Streukapazität, da jetzt die mit dem Gatemetall gefüllte Lücken zwischen benachbarten Bodies schmaler sind. Schließlich wird gezeigt, dass die Polarisationsladung an der Grenzfläche Barrier/Kanal und somit die Elektronendichte im 2DEG durch Erhöhung des Al-Gehalts der AlGaN-Barriere oder durch Nutzung eines anderen Materials für die Barriere (z.B. gitterangepasstes In0.17 Al0.83 N) gesteigert werden kann

Advanced AlGaN/GaN HEMT technology, design, fabrication and characterization

Nowadays, the microelectronics technology is based on the mature and very well established silicon (Si) technology. However, Si exhibits some important limitations regarding its voltage blocking capability, operation temperature and switching frequency. In this sense, Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) devices have the potential to make this change possible. The unique combination of the high-breakdown field, the high-channel electron mobility of the two dimensional electron gas (2DEG), and high-temperature of operation has attracted enormous interest from social, academia and industry and in this context this PhD dissertation has been made. This thesis has focused on improving the device performance through the advanced design, fabrication and characterization of AlGaN/GaN HEMTs, primarily grown on Si templates. The first milestone of this PhD dissertation has been the establishment of a know-how on GaN HEMT technology from several points of view: the device design, the device modeling, the process fabrication and the advanced characterization primarily using devices fabricated at Centre de Recherche sur l'Hétéro-Epitaxie (CRHEA-CNRS) (France) in the framework of a collaborative project. In this project, the main workhorse of this dissertation was the explorative analysis performed on the AlGaN/GaN HEMTs by innovative electrical and physical characterization methods. A relevant objective of this thesis was also to merge the nanotechnology approach with the conventional characterization techniques at the device scale to understand the device performance. A number of physical characterization techniques have been imaginatively used during this PhD determine the main physical parameters of our devices such as the morphology, the composition, the threading dislocations density, the nanoscale conductive pattern and others. The conductive atomic force microscopy (CAFM) tool have been widely described and used to understand the conduction mechanisms through the AlGaN/GaN Ohmic contact by performing simultaneously topography and electrical conductivity measurements. As it occurs with the most of the electronic switches, the gate stack is maybe the critical part of the device in terms of performance and longtime reliability. For this reason, how the AlGaN/GaN HEMT gate contact affects the overall HEMT behaviour by means of advanced characterization and modeling has been intensively investigated. It is worth mentioning that the high-temperature characterization is also a cornerstone of this PhD. It has been reported the elevated temperature impact on the forward and the reverse leakage currents for analogous Schottky gate HEMTs grown on different substrates: Si, sapphire and free-standing GaN (FS-GaN). The HEMT' forward-current temperature coefficients (T^a) as well as the thermal activation energies have been determined in the range of 25-300 ºC. Besides, the impact of the elevated temperature on the Ohmic and gate contacts has also been investigated. The main results of the gold-free AlGaN/GaN HEMTs high-voltage devices fabricated with a 4 inch Si CMOS compatible technology at the clean room of the CNM in the framework of the industrial contract with ON semiconductor were presented. We have shown that the fabricated devices are in the state-of-the-art (gold-free Ohmic and Schottky contacts) taking into account their power device figure-of-merit ((VB^2)/Ron) of 4.05×10^8 W/cm^2. Basically, two different families of AlGaN/GaN-on-Si MIS-HEMTs devices were fabricated on commercial 4 inch wafers: (i) using a thin ALD HfO2 (deposited on the CNM clean room) and (ii) thin in-situ grown Si3N4, as a gate insulator (grown by the vendor). The scientific impact of this PhD in terms of science indicators is of 17 journal papers (8 as first author) and 10 contributions at international conferences

Circuits Techniques for Wireless Sensing Systems in High-Temperature Environments

RÉSUMÉ Dans ce projet, nous proposons de nouvelles techniques d’intégration basées sur la technologie de nitrure de gallium (GaN). Ces techniques permettent de mettre en œuvre un système de transmission de données sans fil entièrement intégré dédié aux capteurs de surveillance pour des applications d'environnement hostile. Le travail nécessite de trouver une technologie capable de résister à l'environnement sévère, principalement à haute température, et de permettre un niveau d'intégration élevé. Le système réalisé serait le premier dispositif de transmission de données basé sur la technologie GaN. En plus de supporter les conditions de haute température (HT) dépassant 600 oC, le système de transmission sans fil attendu devrait fonctionner à travers une barrière métallique séparant le module émetteur du récepteur. Une revue de la littérature sur les applications en environnements hostiles ainsi que sur l'électronique correspondante a été réalisée pour sélectionner la technologie AlGaN/GaN HEMT (transistor à haute mobilité d'électrons) comme une technologie appropriée. Le kit de conception GaN500, fourni par le Conseil national de recherches du Canada (CNRC), a été adopté pour concevoir et mettre en œuvre le système proposé. Cette technologie a été initialement introduite pour desservir les applications radiofréquences (RF) et micro-ondes. Par conséquent, elle n'avait pas été validée pour concevoir et fabriquer des circuits intégrés analogiques et numériques complexes et son utilisation à des températures extrêmes n’était pas validée. Nous avons donc caractérisé à haute température des dispositifs fabriqués en GaN500 et des éléments passifs intégrés correspondants ont été réalisés. Ces composants ont été testés sur la plage de température comprise entre 25 et 600 oC dans cette thèse. Les résultats de caractérisation ont été utilisés pour extraire les modèles HT des HEMT intégrés et des éléments passifs à utiliser dans les simulations. En outre, plusieurs composants intégrés basés sur la technologie GaN500, notamment des NOT, NOR, NAND, XOR, XNOR, registres, éléments de délais et oscillateurs ont été mis en œuvre et testés en HT. Des circuits analogiques à base de GaN500, comprenant un amplificateur de tension, un comparateur, un redresseur simple alternance, un redresseur double alternance, une pompe de charge et une référence de tension ont également été mis en œuvre et testés en HT. Le système de transmission de données mis en œuvre se compose d'un module de modulation situé dans la partie émettrice et d'un module de démodulation situé dans la partie réceptrice.----------ABSTRACT In this project, we propose new integrated-circuit design techniques based on the Gallium Nitride (GaN) technology to implement a fully-integrated data transmission system dedicated to wireless sensing in harsh environment applications. The goal in this thesis is to find a proper technology able to withstand harsh-environments (HEs), mainly characterized by high temperatures, and to allow a high-integration level. The reported design is the first data transmission system based on GaN technology. In addition to high temperature (HT) environment exceeding 600 oC, the expected wireless transmission systems may need to operate through metallic barriers separating the transmitting from the receiving modules. A wide literature review on the HE applications and corresponding electronics has been done to select the AlGaN/GaN HEMT (high-electron-mobility transistor) technology. The GaN500 design kit, provided by National Research Council of Canada (NRC), was adopted to design and implement the proposed system. This technology was initially provided to serve radio frequency (RF) and microwave circuits and applications. Consequently, it was not validated to implement complex integrated systems and to withstand extreme temperatures. Therefore, the high-temperature characterization of fabricated GaN500 devices and corresponding integrated passive elements was performed over the temperature range 25-600 oC in this thesis. The characterization results were used to extract HT models of the integrated HEMTs and passive elements to be used in simulations. Also, several GaN500-based digital circuits including NOT, NOR, NAND, XOR, XNOR, register, Delay and Ring oscillator were implemented and tested at HT. GaN500-based Analog circuits including front-end amplifier, comparator, half-bridge rectifier, full-bridge rectifier, charge pump and voltage reference were implemented and tested at HT as well. The implemented data transmission system consists of a modulation module located in the transmitting part and a demodulation block located in the receiving part. The proposed modulation system is based on the delta-sigma modulation technique and composed of a front-end amplifier, a comparator, a register, a charge pump and a ring oscillator. The output stage of the transmitter is intended to perform the load-shift-keying (LSK) modulation required to accomplish the data transmission through the dedicated inductive link. At the receiver level, three demodulation topologies were proposed to acquire the delivered LSK-modulated signals

Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching it\u27s theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements.;Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETS, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies.;Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal-silicides for the proposed device are considered in this chapter. Finally in Chapter 6 various computer verifications for this work is presented, and in Chapter 7 experimental results to support this work is included