A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Flash-based security primitives: Evolution, challenges and future directions

Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration

Normally-Off Computing Design Methodology Using Spintronics: From Devices to Architectures

Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in post-CMOS switching devices. The foundations of EIC will be advanced from the ground up by extending Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device models to realize SHE-MTJ-based Majority Gate (MG) and Polymorphic Gate (PG) logic approaches and libraries, that leverage intrinsic-non-volatility to realize middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT. Device-level EIC research concentrates on encapsulating SHE-MTJ behavior with a compact model to leverage the non-volatility of the device for intrinsic provision of intermittent computation and lifetime energy reduction. Based on this model, the circuit-level EIC contributions will entail the design, simulation, and analysis of PG-based spintronic logic which is adaptable at the gate-level to support variable duty cycle execution that is robust to brief and extended supply outages or unscheduled dropouts, and development of spin-based research synthesis and optimization routines compatible with existing commercial toolchains. These tools will be employed to design a hybrid post-CMOS processing unit utilizing pipelining and power-gating through state-holding properties within the datapath itself, thus eliminating checkpointing and data transfer operations

Nanochips and medical applications

Ο όρος «νανοτσιπ» αναφέρεται σε ένα ολοκληρωμένο κύκλωμα (τσιπ) με νανοϋλικά και δομές στη νανοκλίμακα (1-100nm). Ένα ολοκληρωμένο κύκλωμα είναι μια συλλογή ηλεκτρονικών εξαρτημάτων, όπως τρανζίστορ, δίοδοι, πυκνωτές και αντιστάσεις. Τα σημερινά τρανζίστορ είναι στη νανοκλίμακα, αλλά μπορούν να τροποποιηθούν με νανοδομές για την κατασκευή βιοαισθητήρων που μπορούν να πραγματοποιούν ανίχνευση βιομορίων, όπως ιόντα, μόρια DNA, αντισώματα και αντιγόνα με μεγάλη ευαισθησία. Υλικά και Μέθοδοι: Πραγματοποιήθηκε συστηματική αναζήτηση βιβλιογραφίας με χρήση των ηλεκτρονικών βάσεων δεδομένων PubMed, Google Scholar και Scopus για την ανάπτυξη και χρήση νανοτσίπ σε ιατρικές εφαρμογές. Για τον προσδιορισμό των σχετικών εργασιών, τα κριτήρια συμπερίληψης αναφέρονται σε άρθρα στην αγγλική γλώσσα, άρθρα βιβλιογραφικού περιεχομένου ή/και έρευνών. Τα κριτήρια αποκλεισμού ήταν άρθρα εφημερίδων, περιλήψεις συνεδρίων και επιστολές. Αποτελέσματα: Τεχνικές in-vivo και in-vitro έχουν χρησιμοποιηθεί για την ανίχνευση μορίων DNA, ιόντων, αντισωμάτων, σημαντικών πρωτεϊνών και καρκινικών δεικτών, όχι μόνο από δείγματα αίματος αλλά και από ιδρώτα, σάλιο και άλλα βιολογικά υγρά. Διαγνωστική εφαρμογή των νανοτσίπ αποτελεί και η ανίχνευση πτητικών οργανικών ενώσεων μέσω τεστ εκπνεόμενης αναπνοής. Υπάρχουν και αρκετές θεραπευτικές εφαρμογές αυτών των συσκευών ημιαγωγών όπως τσιπ διασύνδεσης εγκεφάλου-υπολογιστή για παραλυτικές ή επιληπτικές καταστάσεις, κατασκευή «βιονικών» οργάνων όπως τεχνητός αμφιβληστροειδής, τεχνητό δέρμα και ρομποτικά προθετικά άκρα για ακρωτηριασμένους ή ρομποτική χειρουργική. Συμπέρασμα: Η χρήση των νανοτσίπ στην ιατρική είναι ένας αναδυόμενος τομέας με αρκετές θεραπευτικές εφαρμογές όπως η διάγνωση, η παρακολούθηση της υγείας και της φυσικής κατάστασης και η κατασκευή «βιονικών» οργάνων.Background: The term “nanochip” pertains to an integrated circuit (chip) with nanomaterials and components in the nano-dimension (1-100nm). An integrated circuit is essentially a collection of electronic components, like transistors, diodes, capacitors, and resistors. Current transistors are in the nanoscale but can also be modified with nanostructures like nanoribbons and nanowires to manufacture biosensors that can perform label-free, ultrasensitive detection of biomolecules like ions, DNA molecules, antibodies and antigens. Materials and Methods: A systematic literature search was conducted using the electronic databases PubMed, Google Scholar and Scopus for the development and use of nanochips in medical applications. For the identification of relevant papers, the inclusion criteria referred to articles in the English language, review and/or research articles. The exclusion criteria were newspaper articles, conference abstracts and letters. Results: In-vivo and In-vitro techniques have been used for detection of DNA molecules, ions, antibodies, important proteins, and tumor markers, not only from blood samples but also from sweat, saliva and other biological fluids. Another diagnostic application of nanochips is detection of volatile organic compounds via a breath test. There are also several therapeutic applications of these semiconductor devices like brain-computer interface chips for paralytic or epileptic conditions, manufacture of “bionic” organs like artificial retinas, artificial skin and robotic prostheses for amputees or robotic surgery. Conclusion: The use of nanochips in medicine is an emerging field with several therapeutic applications like diagnostics, health and fitness monitoring, and manufacture of “bionic” organs

Research challenges in Measurement for Internet of Things systems

In this paper, an overview of the research challenges in measurements for the design of Internet of Things (IoT) systems is proposed. To this end, a general architecture of an IoT system is presented, which is specialized according to two key requirements: the power supply capabilities of the infrastructure and the time delay constraints of the application. Guidelines for the design of an IoT system are summarized, and the measurement needs are highlighted. A review of the research contributions is given concerning three main measurement topics: (i) energy-aware data acquisition systems, (ii) localization of mobile IoT nodes, and (iii) precise synchronization protocols

Circuit Techniques for Low-Power and Secure Internet-of-Things Systems

The coming of Internet of Things (IoT) is expected to connect the physical world to the cyber world through ubiquitous sensors, actuators and computers. The nature of these applications demand long battery life and strong data security. To connect billions of things in the world, the hardware platform for IoT systems must be optimized towards low power consumption, high energy efficiency and low cost. With these constraints, the security of IoT systems become a even more difficult problem compared to that of computer systems. A new holistic system design considering both hardware and software implementations is demanded to face these new challenges. In this work, highly robust and low-cost true random number generators (TRNGs) and physically unclonable functions (PUFs) are designed and implemented as security primitives for secret key management in IoT systems. They provide three critical functions for crypto systems including runtime secret key generation, secure key storage and lightweight device authentication. To achieve robustness and simplicity, the concept of frequency collapse in multi-mode oscillator is proposed, which can effectively amplify the desired random variable in CMOS devices (i.e. process variation or noise) and provide a runtime monitor of the output quality. A TRNG with self-tuning loop to achieve robust operation across -40 to 120 degree Celsius and 0.6 to 1V variations, a TRNG that can be fully synthesized with only standard cells and commercial placement and routing tools, and a PUF with runtime filtering to achieve robust authentication, are designed based upon this concept and verified in several CMOS technology nodes. In addition, a 2-transistor sub-threshold amplifier based "weak" PUF is also presented for chip identification and key storage. This PUF achieves state-of-the-art 1.65% native unstable bit, 1.5fJ per bit energy efficiency, and 3.16% flipping bits across -40 to 120 degree Celsius range at the same time, while occupying only 553 feature size square area in 180nm CMOS. Secondly, the potential security threats of hardware Trojan is investigated and a new Trojan attack using analog behavior of digital processors is proposed as the first stealthy and controllable fabrication-time hardware attack. Hardware Trojan is an emerging concern about globalization of semiconductor supply chain, which can result in catastrophic attacks that are extremely difficult to find and protect against. Hardware Trojans proposed in previous works are based on either design-time code injection to hardware description language or fabrication-time modification of processing steps. There have been defenses developed for both types of attacks. A third type of attack that combines the benefits of logical stealthy and controllability in design-time attacks and physical "invisibility" is proposed in this work that crosses the analog and digital domains. The attack eludes activation by a diverse set of benchmarks and evades known defenses. Lastly, in addition to security-related circuits, physical sensors are also studied as fundamental building blocks of IoT systems in this work. Temperature sensing is one of the most desired functions for a wide range of IoT applications. A sub-threshold oscillator based digital temperature sensor utilizing the exponential temperature dependence of sub-threshold current is proposed and implemented. In 180nm CMOS, it achieves 0.22/0.19K inaccuracy and 73mK noise-limited resolution with only 8865 square micrometer additional area and 75nW extra power consumption to an existing IoT system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138779/1/kaiyuan_1.pd

Electronics and Its Worldwide Research

The contributions of researchers at a global level in the journal Electronics in the period 2012–2020 are analyzed. The objective of this work is to establish a global vision of the issues published in the Electronic magazine and their importance, advances and developments that have been particularly relevant for subsequent research. The magazine has 15 thematic sections and a general one, with the programming of 385 special issues for 2020–2021. Using the Scopus database and bibliometric techniques, 2310 documents are obtained and distributed in 14 thematic communities. The communities that contribute to the greatest number of works are Power Electronics (20.13%), Embedded Computer Systems (13.59%) and Internet of Things and Machine Learning Systems (8.11%). A study of the publications by authors, affiliations, countries as well as the H index was undertaken. The 7561 authors analyzed are distributed in 87 countries, with China being the country of the majority (2407 authors), followed by South Korea (763 authors). The H-index of most authors (75.89%) ranges from 0 to 9, where the authors with the highest H-Index are from the United States, Denmark, Italy and India. The main publication format is the article (92.16%) and the review (5.84%). The magazine publishes topics in continuous development that will be further investigated and published in the near future in fields as varied as the transport sector, energy systems, the development of new broadband semiconductors, new modulation and control techniques, and more

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms