440 research outputs found
Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS
Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.
Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes.
With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor
Quantum and spin-based tunneling devices for memory systems
Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits
Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level
Nanostructure based devices are very promising candidates for the emerging
nanotechnologies with advantage in terms of power consumption and functional
density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor
(SET) are the focus of this work. The serious challenges faced by the MOSFET
due to scaling limits can be solved by these devices. NWFET provides better gate
control and overcomes the short channel effects. SET operates in the quantum
confinement regime where the basic operation of MOSFET becomes a challenge.
SET works better when the dimensions are small encouraging the process of scaling
down. Because of these characteristics of the nanodevices, they have achieved a
huge interest from the viewpoint of theoretical as well as applied electronics. The
studies focus on the understanding of the basic transport characteristics of the
devices. The necessity is to develop a model which is efficient, can be used at
circuit level and also provides physical insights of the device.
The first part of this work focuses on developing the model for SET and to
implement it at the circuit level. The transport properties of SET are studied
through quantum simulations. The behavioral characterization of the device is
performed and the effect of different device parameters on the transport is studied.
Furthermore, the impact of gate voltage is analyzed which modulates the current
by shifting the energy levels of the device. After observing the transport through
SET, a model is developed that efficiently evaluates the IV characteristics of the
device. The quantum simulations are used as reference and a huge computational
over-head is achieved while maintaining accuracy. Then the model is implemented
in hardware descriptive language showing its functional variability at circuit level
by designing some logic circuits like AND, OR and FA.
In the second part, the performance of the nanoarrays based on NWFET is
characterized. A device level model is developed to evaluate the gate capacitance
and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices
in nanoarray. A nanoarray implementation for bio-sequence alignment based on
a systolic array is realized and its essential performance is evaluated. The power
consumption, area and performance of the nanoarray implementation are compared
with CMOS implementation. A wide solution space can be explored to find the
optimal solution trading power and performance and considering the technological
limitations of a realistic implementation
ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES
Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices.
Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks.
Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack.
Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation.
Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique.
The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations
Dispositifs innovants à pente sous le seuil abrupte (du TEFT au Z -FET)
Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d effet tunnel. Un modèle analytique combinantl effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z -FET estégalement démontrée sans nécessité de rafraichissement de l information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/ m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte.This thesis is dedicated to studying sharp switching devices, including the tunneling field-effect-transistor(TFET) and a new feedback device we have named the Z2-FET, for low power logic and memory applicationscompatible with modern silicon technology. We have extensively investigated TFETs with various gate oxides,channel materials and structures, fabricated on fully-depleted silicon-on-insulator (FD-SOI) substrates.Low-frequency noise (LFN) measurements were performed on TFETs, showing the dominance of randomtelegraphy signal (RTS) noise, which reveals the tunneling mechanism. An analytical TFET model combiningtunneling and channel transport has been developed, showing agreement with the experimental and simulationresults.We also conceived and demonstrated a new device named the Z2-FET (for zero subthreshold swing andzero impact ionization), which exhibits extremely sharp switching with subthreshold swing SS 4.10-3 A/ mand SS < 60 mV/dec over 7 decades of current, outperforming all silicon-compatible TFETs reported to date.The thesis concludes with future research directions in the sharp-switching device arena.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF
Second year technical report on-board processing for future satellite communications systems
Advanced baseband and microwave switching techniques for large domestic communications satellites operating in the 30/20 GHz frequency bands are discussed. The nominal baseband processor throughput is one million packets per second (1.6 Gb/s) from one thousand T1 carrier rate customer premises terminals. A frequency reuse factor of sixteen is assumed by using 16 spot antenna beams with the same 100 MHz bandwidth per beam and a modulation with a one b/s per Hz bandwidth efficiency. Eight of the beams are fixed on major metropolitan areas and eight are scanning beams which periodically cover the remainder of the U.S. under dynamic control. User signals are regenerated (demodulated/remodulated) and message packages are reformatted on board. Frequency division multiple access and time division multiplex are employed on the uplinks and downlinks, respectively, for terminals within the coverage area and dwell interval of a scanning beam. Link establishment and packet routing protocols are defined. Also described is a detailed design of a separate 100 x 100 microwave switch capable of handling nonregenerated signals occupying the remaining 2.4 GHz bandwidth with 60 dB of isolation, at an estimated weight and power consumption of approximately 400 kg and 100 W, respectively
DESIGN OF MULTI-VALUED LOGIC CELLS USING SINGLE-ELECTRON DEVICES
This thesis proposes a new single-electron tunneling based NDC block and develops an analytical model which can be used for related circuit designs and/or their performance optimization. A piece-wise model is used to describe the I-V characteristics of the proposed NDC block. Four applications based on this NDC block are proposed: (1) Multiple-valued logic static memory cell (2) Schmitt trigger (3) Three-stage ring oscillator (4) ternary full adder using hybrid single-electron transistor and MOS technology. Simulation was done using Cadence Spectre simulator with 180nnm CMOS model and SET MIB macro mode to estimate the performance
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Two-Dimensional Electronic Materials and Devices: Opportunities and Challenges
The unprecedented growth of the Internet of Things (IoT) and the 4th Industrial Revolution (Industry 4.0) not only demands dimensional scaling of device technologies but also new types of applications beyond today’s electronics. Two-dimensional (2D) materials, a group of layered crystals (such as graphene and MoS2) with unique properties, have emerged as promising candidates for IoT and Industry 4.0 since they can, not only extend the scaling with unprecedented performance and energy efficiency but also exhibit high potential for novel electronic devices. However, such nanomaterials suffer from significant challenges in process integration, especially in the modules that involves the formation of interfaces between 2D materials and conventional bulk materials. Thus, realizing high-performance energy-efficient 2D electronic devices has been challenging. This dissertation focuses on understanding the fundamental issues in such 2D materials (such as contacts, interfaces and doping) and in identifying applications uniquely enabled by these materials.First, a comprehensive treatment of metal contacts to 2D semiconductors, which has been a huge hurdle for 2D electronic technologies, will be presented. As a pioneering study, new interface physics originating from the unique dimensionality and surface properties have been revealed [1]. Solutions to minimize contact resistance are described though techniques of interface hybridization [2] and seamless contacts [3], [4]. These techniques transform 2D semiconductors from solely scientifically-interesting materials into high-performance field-effect transistor (FET) technologies, such as MoS2 FETs with record-low contact resistances [5], [6] and WSe2 FETs with record-high drive current and mobility [7]. Beyond metal interfaces, dielectric interface is crucial for preserving the carrier mobility in 2D channels, for which a solution enabled by buffer layers has been proposed [8]. On the other hand, the vertical van der Waals interfaces between 2D and 3D semiconductors, which retain the advantages of pristine ultra-thin 2D films as well as maximized tunneling area/field, have been studied and exploited into a novel beyond-silicon transistor technology – the first 2D channel tunnel FET (TFET) [9], which beat the fundamental limitation in the switching behavior of transistors. Recent results from the engineering of such 2D-3D semiconductor interfaces by surface reduction/passivation are described, showing a significant boost of drive current. While conventional diffusion/ion implantation methods are infeasible for 2D materials, two efficient doping techniques that are specific for 2D materials – surface doping [10], [11] and intercalation doping [12] are presented. The theoretical study of surface doping using ab-initio methods helped develop a novel doping scheme that uniquely exploits the Lewis-base like pedigree of 2D semiconductors without disturbing the structural integrity of the 2D atomic layer configuration [13], as well as a novel electrocatalyst based on MoS2 that achieved record high hydrogen evolution reaction (HER) performance [14]. On the other hand, intercalation doping has been employed to demonstrate graphene based transparent electrodes with the best combination of transmittance and sheet resistance [12], and also the first graphene interconnects with excellent performance, reliability and energy-efficiency [15], [16]. Moreover, by uniquely exploiting the high kinetic inductance and conductivity of intercalation doped graphene, a fundamentally different on-chip inductor has been demonstrated [17], [18], with both small form-factors and high inductance values, that were once thought unachievable in tandem. This 2D technique provides an attractive solution to the longstanding scaling problem of analog/radio-frequency electronics and opens up an unconventional pathway for the development of future ultra-compact wireless communication systems. Finally, a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability is developed for 2D FETs [19]. Subsequently, gate-induced-drain-leakage (GIDL), one of the main leakage mechanisms in FETs especially access transistors, is evaluated for the first time for 2D FETs. The results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.The dissertation concludes with a vision for how a smart life can be realized in the future by harnessing the capabilities of various 2D technologies in the era of IoT and Industry 4.0.[1] J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A computational study of metal-contacts to beyond-graphene 2D semiconductor materials,” in IEEE International Electron Devices Meeting, 2012, pp. 407–410.[2] J. Kang, W. Liu, D. Sarkar, D. Jena, and K. Banerjee, “Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X, vol. 4, no. 3, p. 31005, Jul. 2014.[3] J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for all-graphene monolithic logic circuits,” Appl. Phys. Lett., vol. 103, no. 8, p. 83113, 2013.[4] A. Allain, J. Kang, K. Banerjee, and A. Kis, “Electrical contacts to two-dimensional semiconductors,” Nat. Mater., vol. 14, no. 12, pp. 1195–1205, 2015.[5] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance,” in IEEE International Electron Devices Meeting, 2013, pp. 499–502.[6] J. Kang, W. Liu, and K. Banerjee, “High-performance MoS2 transistors with low-resistance molybdenum contacts,” Appl. Phys. Lett., vol. 104, no. 9, p. 93106, Mar. 2014.[7] W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, and K. Banerjee, “Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.,” Nano Lett., vol. 13, no. 5, pp. 1983–90, May 2013.[8] J. Kang, W. Liu, and K. Banerjee, “Computational Study of Interfaces between 2D MoS2 and Surroundings,” in 45th IEEE Semiconductor Interface Specialists Conference, 2014.[9] D. Sarkar et al., “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, vol. 526, no. 7571, pp. 91–95, Sep. 2015.[10] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” in Proceedings of SPIE, 2013, vol. 8824, p. 88240T–88240T–6.[11] D. Sarkar et al., “Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., vol. 15, no. 5, pp. 2852–2862, May 2015.[12] W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1246–1249, Sep. 2016.[13] S. Lei et al., “Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry,” Nat. Nanotechnol., vol. 11, no. 5, pp. 465–471, Feb. 2016.[14] J. Li, J. Kang, Q. Cai, W. Hong, C. Jian, and W. Liu, “Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering,” Adv. Mater. Interfaces, vol. 1700303, 2017.[15] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Lett., vol. 17, no. 3, pp. 1482–1488, Mar. 2017.[16] J. Jiang, J. Kang, and K. Banerjee, “Characterization of Self - Heating and Current - Carrying Capacity of Intercalation Doped Graphene - Nanoribbon Interconnects,” in IEEE International Reliability Physics Symposium, 2017, p. 6B.1.1-6B.1.6.[17] X. Li et al., “Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect,” in IEEE International Electron Devices Meeting, 2014, p. 5.4.1-5.4.4.[18] J. Kang et al., under review.[19] J. Kang et al., under review
Low Power Memory/Memristor Devices and Systems
This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within
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