Quasi-digital low-dropout voltage regulators uses controlled pass transistors

This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

메모리 어플리케이션을 위한 빠른 과도 응답 성능을 가지는 디지털 낮은 드롭아웃 레귤레이터 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed. To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process. Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.본 논문은 차세대 메모리 시스템에 적용 가능한 빠른 과도 응답 성능을 가지는 디지탈 낮은 드롭아웃 레귤레이터의 설계에 대해 기술한다. 메모리 시스템의 최근 기술들은 높은 전력 밀도와 빠른 데이터 속도를 주된 목표로 하며 이에 맞추어 단기간, 많은 양의 부하 전류 변화를 견디는 파워 컨버터의 필요성이 높아지고 있다. 이에 주기적인 클락 신호에 따라 메모리 데이터 입출력에 유의미한 손상을 발생시키는 전압 강하를 보상하는 해결 방안을 탐색한다. 이를 통해 메모리 시스템이 가지는 제약조건 하에서 빠른 과도 응답 성능을 달성하는 두 가지 구조를 제안한다. 첫 번째 시연으로서, 느린 외부 클락 조건에서 유발되는 디지탈 낮은 드롭아웃 레귤레이터의 과도 응답 성능 저하를 완화시키기 위한 이벤트 주도 방식의 적응형 두 단계 서치 기술을 제안한다. 본 기술은 느린 외부클락에 의존한 루프 동작 시간의 한계를 고리 증폭기 기반 연속 시간 비교기를 통해 해결한다. 또한 자리 이동 레지스터의 구현에 소모되는 비용을 줄이고자 각 레지스터의 제어 장치를 중앙으로 집적시킨 순환형 구조로 설계되었다. 마지막으로 남아있는 조정 에러는 적응방식의 축차 비교형 알고리즘으로 제어하여 교정에 필요한 시간을 최소화하였다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 부하 전압의 빠른 회복 속도와 정정시간을 보임을 확인하였다. 두 번째 시연으로서, 초고속 과도 응답 환경에 적합한 디지털 낮은 드롭아웃 레귤레이터가 설계되었다. 수십~수백 메가헤르쯔 클락의 상승 또는 하강 엣지마다 발생하는 부하 전류 변화를 탐지하고 보상하고 정정하기 위해 기울기 탐지기 기반 coarse 제어기 기술을 제안한다. 시간에 따른 부하 전압 변화의 정도에 따라 차등 보상하는 알고리즘을 적용함으로써 보상 효율을 높였다. 나아가 순람표 기반 자리이동 레지스터는 부하 전류 과도 상태 이후 디지탈 레귤레이터의 빠른 루프 응답 속도를 가능케 하였다. 마지막으로 남은 조정 에러를 제어하는데 있어서 기존 자리이동 레지스터 방식에서 벗어나 빠른 수렴 속도와 높은 해상도를 가지는 양방향 래치 기반 드라이버가 제안되었다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 낮은 부하 축전용량에도 빠른 과도 응답 성능을 통해 효과적인 부하 전압 회복을 이루어 내었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 VARIOUS TYPES OF LDO 4 1.2.1 ANALOG LDO VS. DIGITAL LDO 4 1.2.2 CAP LDO VS. CAP-LESS LDO 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9 2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9 2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12 2.2.1 RESPONSE TIME 13 2.2.1 SETTLING TIME 20 2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21 2.3.1 EVENT-DRIVEN DIGITAL LDO 21 2.3.2 FEEDFORWARD CONTROL 23 2.3.3 COMPUTATIONAL DIGITAL LDO 25 2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27 CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29 3.1 OVERVIEW 29 3.2 PROPOSED DIGITAL LDO 32 3.2.1 MOTIVATION 32 3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36 3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39 3.2.4 STABILITY ANALYSIS 41 3.3 CIRCUIT IMPLEMENTATION 44 3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44 3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49 3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51 3.4 MESUREMENT RESULTS 54 CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62 4.1 OVERVIEW 62 4.2 PROPOSED DIGITAL LDO 64 4.2.1 MOTIVATION 64 4.2.2 ARCHITECTURE OF DIGITAL LDO 66 4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69 4.2.4 FINE-CONTROL LOOP 72 4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74 4.3 CIRCUIT IMPLEMENTATION 77 4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77 4.3.2 SLOPE DETECTOR DESIGN 81 4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84 4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86 4.4 MEASUREMENT(SIMULATION) RESULTS 90 CHAPTER 5 CONCLUSION 95 BIBLIOGRAPHY 97 초 록 109박

Quasi–digital low–dropout voltage regulators uses controlled pass transistors

This article presents a low quiescent current outputcapacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

Time-based low dropout regulator

The low dropout regulator (LDO) is an essential building block for modern integrated circuits. Traditional analog design faces formidable challenges as technology scales down, such as lower supply voltage and channel length modulation. Digital LDOs do not have the problems that analog LDOs have, but they usually have worse performance metrics. Therefore, a time-based LDO is proposed to combine the merits of both analog and digital together. In the end, the LDO achieves 0.6-1 V supply voltage range and 0.5-0.9 V output voltage range. The maximum output current is 50 mA and the worst case transient time is 1.58 μs under 0.6 V supply voltage. The maximum current efficiency is 99.98%

STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Output-capacitorless segmented low-dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.Peer ReviewedPostprint (author's final draft

Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters

Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output stage based on a low dropout regulator stage. For converters such as 12–5V, 5–3.3V and 5–1.5V, the technique provides efficiency improvement factors of 2, 1.33 and 3 respectively, in compared to linear converters with same input-output combinations. In a 5–1.5V SCALDO regulator, using thin profile supercapacitors in the range of fractional farads to few farads, this translates to an approximate end to end efficiency of near 90%. However, there were concerns that this patented technique is merely a variation of well-known switched capacitor (charge pump) converters. This paper is aimed at providing a broad overview of the capability of SCALDO technique with generalized theory, indicating its capabilities and limitations, and comparing the practical performance with a typical switched capacitor converter of similar current capability

Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3 x 10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300 fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is described. Preliminary wafer to wafer distributions as well as yield calculations are given

FPGA Design Techniques for Stable Cryogenic Operation

In this paper we show how a deep-submicron FPGA can be modified to operate at extremely low temperatures through modifications in the supporting hardware and in the firmware programming it. Though FPGAs are not designed to operate at a few Kelvin, it is possible to do so on virtue of the extremely high doping levels found in deep-submicron CMOS technology nodes. First, any PCB component, that does not conform with this requirement, is removed. Both the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad-hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA chip. The FPGA is powered with a supply at several meters distance, causing significant IR drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.Comment: The following article has been submitted to Review of Scientific Instruments. If it is published, it will be available on http://rsi.aip.or