This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

Alarcón Cot, Eduardo José

Martínez García, Herminio

Saberkari, Alireza

English

UPCommons. Portal del coneixement obert de la UPC

Quasi-Digital Low-Dropout Voltage Regulator uses Controlled Pass Transistors  Alireza Saberkari Microelectronics Research Lab.  Department of Electrical Engineering, University of Guilan  Rasht, Iran a_saberkari@guilan.ac.ir Herminio Martínez-García, and Eduard Alarcón-Cot Department of Electronics Engineering Technical University of Catalunya (UPC), BarcelonaTech Barcelona, Spain herminio.martinez@upc.edu   Abstract— This article presents a low quiescent current output-capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively. I.  INTRODUCTION  Nowadays, power management is a very important issue in battery supplied electronic devices. Advanced power management units for system on chip (SoC) applications need multiple voltage regulators to drive various operational blocks [1], [2]. Usually, low-dropout (LDO) voltage regulators are a part of these power management units which have less output ripple in comparison with switching ones. However, in general, they suffer from lower efficiency. The typical structure of a LDO consists of an error amplifier, a pass transistor controlled by the aforementioned error amplifier, a feedback network, and an output capacitor. Most of conventional LDOs use a large off-chip capacitor for stability requirements which cannot be implemented as on-chip capacitors, leading to need output-capacitorless LDOs for SoC applications [3].  Some papers in connection with output-capacitorless LDOs have been reported in recent years [4-9]. In this way, the reported LDO in [4] uses a capacitor multiplier stage as a separate one to improve the dynamic performance of the LDO, while increases its power consumption. The LDOs in [5] and [6] have simple structure based on the flipped voltage follower (FVF). However, they suffer from weak load and line regulations. In [7], the proposal of an ultra fast transient response LDO has the problem of high consumption and significant high quiescent current. Thus, it is not appropriate for low power applications and battery-based devices. The LDO in [8] uses a pole-zero tracking frequency compensation technique in which an “adaptive” zero created thanks to a variable linear resistance cancels the regulator output pole. However, mismatch can degrade the compensation strategy. Finally, Nested-Miller compensation technique with a programmable capacitor array was used in [9] in order to provide good phase margin and control the damping factor. Nevertheless, the output voltage of LDO changes dramatically when the load current changes. In addition, recently, some digital LDOs with off-chip output capacitor have been reported. The LDO in [10] can deliver only 200 µA current to the load while consumes 2.7 µA quiescent current and has one array of 256 power transistors. On the other hand, [11] shows a digitally controlled LDO regulator in which the output voltage variation and settling time to the load transient is quite large, 700 mV and 1.77 ms, respectively. The quiescent current of the LDO in [12] is 164.5 µA, which can discharge fast the battery voltage.    In typical LDO circuits, a very large size pass transistor is used to support the low dropout performance and high current demanding loads. This involves that a large capacitance will be created at the gate of pass transistor, making a limit on slew-rate at this node. Additionally, since the charge and discharge process of such a large capacitor takes a long time, the feedback loop reaction against fast load variations will be slow, destroying feedback loop response of the circuit. Such a large size device is designed for maximum load current. However, this maximum current is not needed for all times, since the LDO is in standby mode in most of the time [8]. Therefore, it can be possible to break up the pass transistor to smaller sizes and control their performance according to the load demands. This paper presents an output-capacitorless LDO in which the control of the pass transistor sizes is carried out in a quasi-digital manner.  Section II describes the pass transistor breakup criterion to smaller sizes. The proposed LDO architecture is presented in section III. Finally, circuit characterization and conclusion are in sections IV and V, respectively. II. PASS TRANSISTOR BREAKUP CRITERION As mentioned before, using a large pass transistor creates a large capacitance at its gate terminal, which takes a long time to charge and discharge. Therefore, the output voltage variations to load current and/or input voltage transients will be increased; that is, the transient load and lines regulations get worse. Regarding load transient response, a breakup criterion (BC, expressed in mV/mA) is defined here, as Eq. (1), by evaluating the maximum output voltage variations to different load current variation steps for the maximum size power transistor in order to find a suitable load current boundary for breaking up the large pass transistor into smaller ones.              Maximum Ouput Voltage VariationsLoad Current VariationsBC             (1) It should be mentioned that each pass transistor needs its own control circuitry, adding more power dissipation and complexity. As a consequence, a trade-off should be considered between number of pass transistors, power consumption, and complexity. Fig. 1(a) shows a simple LDO regulator, which consists of a cascode error amplifier with a current buffer-based compensation scheme, a pass transistor, and feedback network. Fig. 1(b) shows the defined BC versus different load current steps for the LDO shown in Fig. 1(a). As it can be seen, the maximum output voltage variation occurs at low load conditions (less than 1 mA). Therefore, this current range is selected as a boundary for breaking up the pass transistor, and one transistor is utilized to cover this current range. Additionally, with regards to Fig. 1(a), other steps of load current variations cause less variations at the output voltage and so higher load currents can be covered by another pass transistor. Consequently, the designed LDO regulator will have two pass transistors while second one turns on when the load current is higher than 1 mA. III. THE PROPOSED LDO ARCHITECTURE Fig. 2 shows the transistor level schematic of the proposed LDO. Transistors M1–M6 make the cascode error amplifier. Capacitor Cb and transistor M4 form a current buffer for frequency compensation. Rf1 and Rf2 are the feedback network resistors and Cout is the output capacitor. In order to achieve high current efficiency, especially at low load currents, the proposed LDO is designed with a small bias current Ib, and extra bias currents for higher loads are provided through a dynamic biasing approach by transistor M7 and load current sampling network M8–M9. Transistors MP1 and MP2 are as pass transistors and responsible for delivering currents to the load. Transistor MP1, with the size of 50 µm/0.35 µm, is used for low load current steps (less than 1 mA, according to the BC obtained in previous section) and MP2, with the size of 3500 µm/0.35 µm, provides the current for loads higher than 1 mA. Transistors M12 and M13 act as a level shifter to provide a suitable control signal from the error amplifier to the pass transistor MP2. Finally, transistors M10 and M11 control the second pass transistor gate voltage with respect to the output load current. The mechanism of voltage regulation is discussed in the following. In case that the load current increases, the output voltage is prone to drop. Thus, the gate-source voltage of M1 decreases. As a result, the drain current of M1, M3, M5, and M6 will be decreased, and that of M2 and M4 will be increased causing the gate voltage of MP1 to decrease and more current will source to the load. When the load current achieves more than the boundary, the gate voltage of M10 and M11 will be increased through the load current sampling network (transistors M8–M9) and, therefore, their drain voltage drops turning on the second pass transistor MP2 to deliver more current to the load. The higher the load current is, the lower the drain voltage of M10 and M11 is, and as a result, the sufficient current will be deliver to the load through MP2. In no-load condition, M10 is in triode and M11 is cut-off. In full-load condition, both transistors are in saturation. An analogous mechanism occurs when the load current decreases.  (a)  (b) Figure 1.  (a) Circuit schematic of the simple LDO voltage regulator. (b) Breakup criterion (BC) for the LDO of Fig. 1(a). Fig. 3 shows the small signal model of the proposed LDO regulator in which R1 and C1 are the output resistance and equivalent capacitance at the output node of error amplifier, respectively. Rout is the output resistance of the LDO which equals LoadffpMoo RRRrR ||)(|| 211,2  for load currents lower than the boarder line (1 mA, in the considered case), and equals LoadffpMopMoo RRRrrR ||)(|||| 212,1,3   for load currents more than that. Additionally, when the load current is lower than the boarder line, the dashed line part will not operate, and, for load currents more than that, this part will be added to the circuit and the pass transistor size will be increased. If the level shifter (buffer) stage is designed carefully so that its output pole is crated at higher frequencies, this stage can be ignored for small signal analysis and, hence, for higher load currents, the effective transconductance of pass transistors are sum of the gmp1 and gmp2 which approximately equals gmp2 (notice that gmp2 is much greater than gmp1). Carrying out small signal analysis on the circuit, the transfer function is shown in Eq. (2).  Figure 2.  Schematic of the proposed LDO.  Figure 3.  Small signal model of the proposed LDO.                         )1)(1)(1()1(32110PsPsPsZsAAV ,                  (2) where, the feedback factor, DC gain, pole-zero positions, and unity-gain frequency are as following:             outmpm RRggA 110              212fffRRR           (3)              outbmp RRCgP111              bmCgZ 41             (4)              outmpbCCgCP12                         bmCgP 43             (5)                                       bmT Cg 1                                       (6) For load currents lower than the boundary, gmp1 and Ro2 are represented, respectively, by gmp and Rout in Eqs. (3)–(6), while gmp2 and Ro3 are represented for higher load currents. As it is obvious, the pole P3 and the zero Z1 can cancel each other. In addition, the pole P2 moves to higher frequencies by a factor of Cb/C1, which guarantees the LDO stability. Fig. 4 shows the open loop frequency response of the proposed LDO regulator with Cb=2 pF and Cout=100 pF. As it can be seen, the LDO is stable over the entire load current range, and the phase margins for no-load and full-load conditions are 91º and 66º, respectively. Additionally, the effect of process variation (slow-slow and fast-fast) on the frequency response was checked which indicates that the LDO has less sensitivity to the process variations.   Figure 4.  Open loop frequency response of the proposed LDO for no-load and full-load conditions. IV. CIRCUIT CHARACTERIZATION The proposed LDO topology has been designed to source a load current between 0-100 mA and the obtained results correspond to HSPICE post simulations in a 0.35 µm CMOS process. The dropout voltage of the LDO was set to 200 mV for 3–3.5 V input voltage. The total quiescent current of the LDO at no-load and full-load conditions are 7.6 and 50 µA, respectively. The power supply ripple rejection (PSR) of the LDO at 10 kHz frequency is –57 and –44 dB under no-load and full-load conditions, respectively. In addition, the load and line regulations are 0.23 mV/mA and 1.5 mV/V, respectively. Fig. 5 shows the output voltage transient response of the LDO for different load current changes with rise and fall times of 1 µs. As it is obvious, the maximum output voltage deviation from its desired value is 270 mV which occurs at 20 µs with duration of only 1.1 µs. Line transient response of the LDO is shown in Fig. 6, in which the line voltage changes between 3 V and 3.5 V with rise and fall times of 1 µs. It demonstrates that the maximum output variation is only 12 mV and its settling time is 2 µs.   Table I provides a performance comparison between the proposed LDO and recent works. In order to have a fair and coherent comparison, other LDOs except [12] are simulated in HSPICE and the table results correspond to their simulations. The results of the proposed LDO without controlling the pass transistor are also included. As it can be seen, both the output voltage variation and settling time will be increased without controlling the pass transistor. The figure of merit ( 2 max,outQoutout IICVFOM  ) used in [7] is adopted here to compare the transient response of different LDOs. Notice that smaller FOM shows better transient operation. As it can be seen, controlling the power transistor size with regards to the load current, leads to better transient LDO performance.  Figure 5.  Load transient response of the proposed LDO.  Figure 6.  Line transient response of the proposed LDO. TABLE I.  PERFORMANCE COMPARISON This Work Parameters [5] [9] [11] [12] Without Control With Control Tech (µm) 0.35 0.35 0.35 65 nm 0.35 0.35 Vin (V) 1.2 2 0.9  1.1 3 3 Vout (V) 1  1.8 0.7  0.5-1 2.8 2.8 Iout (mA) 0-50 0-150 0-50 0-100 0-100 0-100 IQ (µA) 95 20 4.7 164.5 6 7.6 Cout (pF) 20 100 100 4.5 nF  off-chip 100 100 Tsettle (µs) 1.4 90>  1.77 ms N.A. 16 ≈4.7 ∆Vout (mV) 200 540 700 120 500 270 CE (%) 99.8 99.9 99.9 99.8 99.9 99.9 FOM (fs) 152 48 131.6 8883 30 20.52 V. CONCLUSION This paper presents an output-capacitorless quasi-digital CMOS LDO regulator. The pass transistor of the LDO is broken up to two smaller sizes, one for low currents and another one for high currents, based on a breakup criterion which considers the maximum output voltage variations to different load current steps. Post-layout simulation results in a 0.35 µm CMOS process show 46% and 69% improvement on the output voltage variations and settling time, respectively, in comparison with the case that the power transistor is used in its maximum size. ACKNOWLEDGMENT This work has been partially supported by the Spanish Ministerio de Economía y Competitividad by project DPI2013-47799-C2-2-R. REFERENCES [1] D. D. Buss, “Technology in the Interest Age,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC’02), Dig. Tech. Papers, Feb. 2002, pp. 12-13.  [2] A. Saberkari, H. Martinez, and E. Alarcon, “Fast Transient Response CFA-Based LDO Regulator,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’012), May 2012, pp. 3150-3153. [3] A. Saberkari, R. Fathipour, H. Martinez, A. Poveda, and E. Alarcon, “Output-Capacitorless CMOS LDO Regulator Based on High Slew-Rate Current-Mode Transconductance Amplifier,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’013), May 2013, pp. 1484-1487. [4] R. J. Millikan, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full On-Chip CMOS Low-Dropout Voltage Regulator,” IEEE Trans. Circuit Syst. I, vol. 54, no. 9, pp. 1879-1890, Sept. 2007. [5] T. Y. Man, K. L. Leung, C. Y. Leung, P. K. Mok, and M. Chan, “Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SOC, “IEEE Trans. Circuit Syst. I, vol. 55, no. 5, pp.1392-1401, Jan. 2008. [6] P. Y. Or and K. N. Leung, “An Output-Capacitorless Low-Dropout Regulator with Direct Voltage-Spike Detection,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 458-466, Feb. 2010. [7] P. Hazucha, T. Karnik, B. Bloechel, C. Parsons, C. Parsons, D. Finan, and S. Borker, “Area-Efficient Linear Regulator with Ultra-Fast Load Regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933-940, Apr. 2005. [8] K. C. Kwok and P. K. T. Mok. “Pole-Zero Tracking Frequency Compensation for Low-Dropout Regulator,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’02), May 2002, pp. 735-738. [9] W. J. Huang and S. I. Liu, “Capacitor-Free Low-Dropout Regulators Using Nested Miller Compensation with Active Resistor and 1-bit Programmable Capacitor Array,” IET Circuits Devices Syst., vol. 2, no. 3, pp. 306-316, 2008. [10] Y. Okuma et.al., “0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS,” IEICE Trans. Electron., vol. E94-C, no. 6, pp. 938-944, Jun. 2011. [11] Y. L. Lo and W. J. Chen, “A 0.7 V Input Output-Capacitor-Free Digitally Controlled Low-Dropout Regulator with High Current Efficiency in 0.35 µm CMOS Technology,” Microelectronics Journal, vol. 43, no. 62, pp. 756-765, Aug. 2012. [12] W. C. Hsieh and W. Hwang, “All Digital Linear Voltage Regulator for Super-to-Near Threshold Operation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 6, pp. 989-1001, Jun. 2012.   

Quasi-digital low-dropout voltage regulators uses controlled pass transistors

https://upcommons.upc.edu/bitstream/2117/101342/1/TCC22.pdf

Quasi-digital low-dropout voltage regulators uses controlled pass transistors

Abstract

Similar works

Full text

Available Versions

UPCommons. Portal del coneixement obert de la UPC