Virtualization for a Network Processor Runtime System

The continuing ossification of the Internet is slowing the pace of network innovation. Network diversification presents one solution to this problem, by virtualizing the network at multiple layers. Diversified networks consist of a shared physical substrate, virtual routers (metarouters), and virtual links (metalinks). Virtualizing routers enables smooth and incremental upgrades to new network services. Our current priority for a diversified router prototype is to enable reserved slices of the network for researchers to perform repeatable, high-speed network experiments. General-purpose processors have well established techniques for virtualization, but do not scale efficiently to multi-gigabit speeds. To achieve these speeds, we employ network processors (NPs), typically consisting of multicore, multi-threaded processors with asymmetric, heterogeneous memories. The complexity and lack of hardware thread isolation in NP’s, combined with a lack of simple programming models, creates numerous challenges for effective sharing between metarouters. In this paper, we detail strategies for enabling NP virtualization at the link, memory, and processor levels, to better enable a research infrastructure for network innovation

Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs

Multicore architectures offer an amount of parallelism that is often underutilized, as a result these underutilized resources become a liability instead of advantage. Inefficient resource sharing on the chip can have a negative impact on the performance of an application and may result in greater energy consumption. A large body of research now focuses on reconfigurable multicore architectures in order to support algorithms to find optimal solutions for improved energy and throughput balance. An ideal system would be able to optimize such reconfigurable systems to a level that optimum resources are allocated to a particular workload and all the other underutilized resources remain inactive for greater energy savings. This paper presents a fuzzy logic based reconfiguration engine targeted to optimize a multicore architecture according to the workload requirements for optimum balance between power and performance of the system. The proposed fuzzy logic reconfiguration engine is designed around a 16-core SCMP architecture comprising of reconfigurable cache memories, power gated cores and adaptive on-chip network routers for minimizing leakage energy effects for inactive components. A coarse grained architecture was selected for being able to reconfigure faster, thus making it feasible to be used for runtime adaptation schemes. The presented architecture is analyzed over a set of OpenMP based parallel benchmarks and results show significant energy savings in all cases

Performance Regulation and Tracking via Lookahead Simulation: Preliminary Results and Validation

This paper presents an approach to target tracking that is based on a variable-gain integrator and the Newton-Raphson method for finding zeros of a function. Its underscoring idea is the determination of the feedback law by measurements of the system's output and estimation of its future state via lookahead simulation. The resulting feedback law is generally nonlinear. We first apply the proposed approach to tracking a constant reference by the output of nonlinear memoryless plants. Then we extend it in a number of directions, including the tracking of time-varying reference signals by dynamic, possibly unstable systems. The approach is new hence its analysis is preliminary, and theoretical results are derived for nonlinear memoryless plants and linear dynamic plants. However, the setting for the controller does not require the plant-system to be either linear or stable, and this is verified by simulation of an inverted pendulum tracking a time-varying signal. We also demonstrate results of laboratory experiments of controlling a platoon of mobile robots.Comment: A modified version will appear in Proc. 56th IEEE Conf. on Decision and Control, 201

Fuzzy logic based energy and throughput aware design space exploration for MPSoCs

Multicore architectures were introduced to mitigate the issue of increase in power dissipation with clock frequency. Introduction of deeper pipelines, speculative threading etc. for single core systems were not able to bring much increase in performance as compared to their associated power overhead. However for multicore architectures performance scaling with number of cores has always been a challenge. The Amdahl's law shows that the theoretical maximum speedup of a multicore architecture is not even close to the multiple of number of cores. With less amount of code in parallel having more number of cores for an application might just contribute in greater power dissipation instead of bringing some performance advantage. Therefore there is a need of an adaptive multicore architecture that can be tailored for the application in use for higher energy efficiency. In this paper a fuzzy logic based design space exploration technique is presented that is targeted to optimize a multicore architecture according to the workload requirements in order to achieve optimum balance between throughput and energy of the system

On Designing Multicore-aware Simulators for Biological Systems

The stochastic simulation of biological systems is an increasingly popular technique in bioinformatics. It often is an enlightening technique, which may however result in being computational expensive. We discuss the main opportunities to speed it up on multi-core platforms, which pose new challenges for parallelisation techniques. These opportunities are developed in two general families of solutions involving both the single simulation and a bulk of independent simulations (either replicas of derived from parameter sweep). Proposed solutions are tested on the parallelisation of the CWC simulator (Calculus of Wrapped Compartments) that is carried out according to proposed solutions by way of the FastFlow programming framework making possible fast development and efficient execution on multi-cores.Comment: 19 pages + cover pag