Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

Harmonic balance surrogate-based immunity modeling of a nonlinear analog circuit

A novel harmonic balance surrogate-based technique to create fast and accurate behavioral models predicting, in the early design stage, the performance of nonlinear analog devices during immunity tests is presented. The obtained immunity model hides the real netlist, reduces the simulation time, and avoids expensive and time-consuming measurements after tape-out, while still providing high accuracy. The model can easily be integrated into a circuit simulator together with additional subcircuits, e.g., board and package models, as such allowing to efficiently reproduce complete immunity test setups during the early design stage and without disclosing any intellectual property. The novel method is validated by means of application to an industrial case study, being an automotive voltage regulator, clearly showing the technique's capabilities and practical advantages

Diamond Detectors for the TOTEM Timing Upgrade

This paper describes the design and the performance of the timing detector developed by the TOTEM Collaboration for the Roman Pots (RPs) to measure the Time-Of-Flight (TOF) of the protons produced in central diffractive interactions at the LHC. The measurement of the TOF of the protons allows the determination of the longitudinal position of the proton interaction vertex and its association with one of the vertices reconstructed by the CMS detectors. The TOF detector is based on single crystal Chemical Vapor Deposition (scCVD) diamond plates and is designed to measure the protons TOF with about 50 ps time precision. This upgrade to the TOTEM apparatus will be used in the LHC run 2 and will tag the central diffractive events up to an interaction pileup of about 1. A dedicated fast and low noise electronics for the signal amplification has been developed. The digitization of the diamond signal is performed by sampling the waveform. After introducing the physics studies that will most profit from the addition of these new detectors, we discuss in detail the optimization and the performance of the first TOF detector installed in the LHC in November 2015.Comment: 26 pages, 18 figures, 2 tables, submitted for publication to JINS

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

UWB implementation and utilization in mPOS device

Abstract. This thesis investigates the possible implementation and utilization of ultra-wideband (UWB) technology in a handheld device that serves as a sales system. The basic information of UWB technology based on theory is introduced, such as history, benefits and challenges, current standards, and the most common use cases. The general requirements and the planned use cases for UWB technology are presented to narrow the scope of the thesis. The thesis covers status of the current suppliers of UWB components and reasonings of the selection of a UWB chip and antennas for this thesis. Measurements are performed with the UWB chip, the UWB antennas and the entire UWB system implementation to verify that the requirements are met, and the technology works as designed. Based on theory and measurement results, it is demonstrated that both the implementation and utilization of UWB in the handheld device with the desired characteristics can be done

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

Characterisation of on-chip electrostatic discharge waveforms with sub-nanosecond resolution: design of a differential high voltage probe with high bandwidth

Bliksem werd tot aan de ontdekking van de bliksemafleider (18e eeuw) gezien als een van de gevaarlijkste bedreigingen voor het stadsleven. Door het gebruik van micro-elektronica werden ingenieurs gewaar dat ditzelfde fysische verschijnsel, elektrostatische ontlading of ESD genoemd, zich ook op microscopische schaal voordoet. In de jaren zeventig was meer dan 30% van al het chipfalen te wijten aan ESD. Om dit tegen te gaan werd met het onderzoek naar ESD-protecties en -meetsystemen aangevangen. Om meer informatie over het gedrag van een ESD-protectie te verkrijgen wordt een ESD-puls op dit systeem losgelaten. Het antwoord van de protectie op deze puls wordt dan bepaald m.b.v. spannings- en stroomgolfvormmetingen. In dit werk wordt een nieuwe nauwkeurige ESD-golfvormmeettechniek voorgesteld die directe metingen op protecties kan uitvoeren. De karakterisering van ESD-golfvormen op chip wordt enorm bemoeilijkt door de grote hoeveelheid elektromagnetische interferentie die de ESD-puls veroorzaakt. Dit wordt omzeild door het gewenste signaal naar een veilige omgeving te transporteren, waar een standaard meettoestel de meting kan uitvoeren. Dit transport wordt gerealiseerd m.b.v. optische communicatie, wat immuun is voor elektromagnetische interferentie. Zo kan nauwkeurige in-situ-informatie worden verkregen waarmee de ESD-protecties in de toekomst verbeterd kunnen worden.Up to the 18th century, lightning was considered one of nature’s most dangerous threats in city life. This all ended with the lightning rod, protecting thousands of homes during lightning storms. The large-scale use of microelectronics has made engineers aware of the same physical phenomenon occuring on a microscopic scale. This phenomenon is called electrostatic discharge or ESD. In the seventies, more than 30% of all chip failure was attributed to static electricity. To counter this effect, the research for on-chip ESD protections was born. Today ESD is a buzzing line of research, as with new and faster chip technologies comes a higher ESD vulnerability. This makes ESD protection and measurement increasingly important. Although ESD is now a major subject in chip design, it copes with a lack of accurate device models. To gain more information on the exact operation of an ESD protection, an ESD pulse is unleashed upon this device. The response of the protection on this pulse is then assessed by performing voltage or current waveform measurements. This work presents a waveform measurement technique able to accurately perform direct measurements on the ESD protection. Due to the high amount of electromagnetic interference caused by the ESD pulse, direct waveform characterisation near the protection is hard. This is solved by transporting the target signal into a clean area, where the measurement is performed by standard lab equipment. The key is that this transportation is realized by means of optical communication, which is immune to electromagnetic interference. This way, accurate in situ information can be used to protect tomorrow’s chips

Optocoupler Integration of LTCC-based Gate Driver in a SiC Power Module

The growing demand for electrical energy in today’s industrialized economy has driven the need for innovative approaches to meet diverse application requirements. Notably, advancements have been made in the field of power electronic systems, as reliable power electronic converters are essential for managing multiple power sources and loads. However, the development of these systems poses challenges related to power device switching speed, system weight and size, and power losses. The integration of a gate driver into a SiC power module offers a solution to many of these challenges, thereby driving the advancement of electrical power density expansion. An LTCC-based gate driver with an LTCC-based optical isolator was developed and integrated into a fabricated 1.2kV SiC power module. This development was done specifically for high temperature applications as part of a wider research on the reliability of the integrated power module at higher temperatures. Therefore, this high temperature gate driver integrated SiC power module was tested from 25oC to 200oC. Double pulse testing of the fabricated integrated SiC power module was done to characterize the switching performance of the power module. The test results indicate a minimal voltage overshoot of approximately 3.5V during both the turn-on and turn-off periods. Additionally, the current overshoot ranges from ~5A to ~8A as the temperature increases from 25oC to 200oC. The results show good switching performance resulting in minimal losses over higher temperatures. Therefore, with these results, the integrated SiC power module can enhance better power density, and lower losses even in high temperature applications