Power-compute co-design for robust pervasive IoT applications

PhD ThesisThe modern development of internet of things (IoT) requires the IoT devices to be more compact and energy autonomous. Many of them require to be able to operate with unstable and low power supplies that come from various energy sources such as energy harvesters. This creates a challenge for building IoT devices that need to be robust to energy variations. In this research we propose methods for improving energy characteristics of IoT devices from the perspective of two main challenges: (i) improving the efficiency and stability of power regulators, and (ii) enhancing the energy robustness of the IoT devices. The existing design methods do not consider these two aspects holistically. One important feature of our approach is holistic use of event-based, temporal representation of data, which involves using asynchronous techniques and duty-cycle-based encoding. For power regulation we use switched-capacitor converters (SCC) because they offer compactness and ease of on-chip implementation. In this research we adapt the existing methods and develop new techniques for SCC design based on asynchronous circuits. This allows us to improve their performance and stability. We also investigate the methods of parasitic charge redistribution, and apply them to self-oscillating SCC, improving their performance. The key contribution within (i) is development of the methods of SCC design with improved characteristics. The majority of novel IoT systems are shifting towards the “AI at the edge” vision, for example, involving neural networks (NN). We consider a perceptron-based neural network as a typical IoT computing device. In our research we propose a novel NN design approach using the principle of pulse-width modulation (PWM). PWMencoded signals represent information with their duty cycle values which may be made independent of the voltages and frequencies of the carrier signals. As a result, the device is more robust to voltage variations, and, thus, the power regulation can be simplified. This is the second major contribution addressing challenge (ii). The advantages of the proposed methods are validated with simulations in the Cadence environment. The simulations demonstrate the operation of the designed power regulators, and the improvements of their efficiency. The simulations also demonstrate the principle of operation of the PWM-based perceptron and prove its power and frequency elasticity. The thesis gives future research directions into a deeper study of the holistic co-design of a variation-robust power-compute paradigm and its impact on developing future IoT applications

Design of Readout Electronics for the DEEP Particle Detector

Along with electromagnetic radiation, the Sun also emits a constant stream of charged particles in the form of solar wind. When these particles enter Earth’s atmosphere through a process known as particle precipitation, they can through a series of chemical reactions produce N Ox and HOx gases. These gases are greenhouse gases and deplete the ozone in the mesosphere and upper stratosphere. It is important to quantify the rate of production of these gases to model the potential climate impact. Existing particle detectors in space are suboptimal because they cannot determine the energy flux and pitch angle distribution of precipitating particles. The primary scientific objective of the DEEP project is to design a particle detector instrument that is specifically designed for particle precipitation measurements. This thesis investigates different data acquisition schemes for handling the signal from a pixel detector. The chosen approach is measuring the width of a shaped pulse to quantify the energy of the particle. Known as Time-over-Threshold, a detector circuit board is designed featuring high-speed comparators as threshold discriminators and the NG-MEDIUM FPGA from NanoXplore to implement the data acquisition. Digitizing the comparator pulse width is done with a Time-to-Digital converter (TDC) implemented in the FPGA fabric. Since the difference in pulse width is small for different energies, a high conversion resolution is required. Two high-resolution TDCs are designed and compared, both of which feature a digital counter and a method of interpolating the counter clock period. The first interpolation method applies the use of a multitapped delay line implemented with hard carry chain resources, and the second method oversamples the input with several equally off-phase sampling clocks. A resolution of 302 ps and a differential non-linearity of 3.26 was achieved with the delay line TDC clocked at 100 MHz. An automatic statistical calibration scheme is included to determine the actual delays of the delay line, utilizing a second asynchronous clock to generate uniformly distributed hits. The asynchronous oversampler resolution is clock frequency dependent and provides a 4-fold improvement to the clock period. The differential nonlinearity approaches zero with close matching of the off-phase clocks and operating frequency. A complete firmware design for the data acquisition and rocket telemetry of the detector is proposed and demonstrated. A simulation of the firmware utilizing each TDC topology is conducted and the delay line TDC is demonstrated to be the most accurate at all operating frequencies and thus the recommended TDC for the DEEP data acquisition.Masteroppgave i fysikkPHYS399MAMN-PHY

Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 173-183).Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures designed for energy constrained wireless applications. First, as a case study, a highly digital, voltage scalable flash ADC is presented. The flash ADC, implemented in 0.18 [mu]m CMOS, leverages redundancy and calibration to achieve robust operation at supply voltages from 0.2 V to 0.9 V. Next, the thesis expands in scope to describe a pulsed, noncoherent ultra-wideband transceiver chipset, implemented in 90 nm CMOS and operating in the 3-to-5 GHz band. The all-digital transmitter employs capacitive combining and pulse shaping in the power amplifier to meet the FCC spectral mask without any off-chip filters. The noncoherent receiver system-on-chip achieves both energy efficiency and high performance by employing simple amplifier and ADC structures combined with extensive digital calibration. Finally, the transceiver chipset is integrated in a complete system for wireless insect flight control.(cont.) Through the use of a flexible PCB and 3D die stacking, the total weight of the electronics is kept to 1 g, within the carrying capacity of an adult Manduca sexta moth. Preliminary wireless flight control of a moth in a wind tunnel is demonstrated.Ph.D

Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

Digital signal processor fundamentals and system design

Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution

Design, implementation, and verification of an FPGA-based control system for a permanent-magnet motor drive built upon a three-phase four-level active-clamped inverter

At the present time, a DE0 board from Terasic/Altera, which includes a Field Programmable Gate Array (FPGA) Cyclone III, is used to control a three-phase four-level active-clamped inverter which drives a permanent-magnet motor. The project consists in designing a new FPGA-based control system that substitutes the current control system based on the DE0 board. The novel control system will consist of a single board containing a new FPGA more suitable for the specific application, the analog-to-digital converters, and all the necessary auxiliary circuitry. The FPGA content wi[ANGLÈS] The present work summarizes the work and knowledge acquired by the author during its Master’s Thesis in the Research Group in Power Electronics, GREP. The development is based on the Multilevel Active-Clamped (MAC) power converter prototype, which was initially developed by GREP. Serving as a great introduction to the multilevel converter state-of-the-art, the prototype was tested and it was proved the need for a custom FPGA-based control platform board to drive a PMSM. The design of the board is then performed following the requirements established by the research group and the results obtained from the initial tests. Issues as power decoupling, signal conditioning and grounding strategies are discussed in the following chapters.[CASTELLÀ] La memoria aquí presentada recoge el trabajo y el conocimiento adquirido por el autor durante la elaboración de su tesis de Máster dentro del Grupo de Investigación en Electrónica de Potencia de la Universidad Politécnica de Cataluña, GREP. El trabajo elaborado se desarrolla en torno al prototipo, previamente desarrollado por los miembros del GREP, de un convertidor de potencia multinivel de tipo MAC (Multilevel Active-Clamped). La familiarización con los últimos avances en conversores multinivel se lleva a cabo mediante la fase de pruebas experimentales con este dispositivo, que a su vez demuestran la necesidad de diseñar una placa controladora específica basada en FPGA para mover un motor de imanes permanentes. Esta placa de control se diseña siguiendo los requisitos establecidos por el GREP y las necesidades surgidas en la fase de experimentación. En los capítulos del trabajo se tratan temas como el desacoplo de la alimentación, acondicionamiento de señales o metodologías de diseño de planos de masa.[CATALÀ] La memòria aquí presentada recull el treball i el coneixement adquirit per l'autor durant l'elaboració de la seva tesi de Màster dins del Grup de Recerca en Electrònica de Potència de la Universitat Politècnica de Catalunya, GREP. El treball es desenvolupa en torn al prototipus, prèviament desenvolupat pels membres del GREP, d'un convertidor de potència multinivell de tipus MAC (Multilevel Active-Clamped). La familiarització amb els darrers avanços en convertidors multinivell s'ha dut a terme mitjançant la fase de proves experimentals amb aquest prototipus, les quals han demostrat la necessitat de dissenyar una placa controladora específica basada en FPGA per controlar un motor d'imants permanents. Aquesta placa de control s'ha dissenyat seguint els requisits establerts pel GREP i les necessitats aparegudes en la fase d'experimentació. En els capítols del treball es tracten temes com el desacoblament de l'alimentació, condicionament de senyals o metodologies de disseny de plans de massa

Microprocessor- Oriented Algorithms for Data Communications

Data modem design has attracted a lot of scientific and commercial interest for more than three decades now. The field is important from a scientific point of view, since reliable data communications require very sophisticated solutions to many associated problems. From a commercial point of view its importance arises from the ever- rising needs for Computer networking and distributed processing in general. Modem algorithms are real-time in nature, so adequate technological support is important for modem design development. Advances in VLSI are opening new possibilities in this area and current trends toward integration of computing and communications are placing new demands on its further development. One can say that data modem design is entering its renaissance and this fact was our motivation in preparing this text. The objective is to bridge the gap between the increasing number of published papers on modem design and implementation, and the rapidly growing interest in the field. Included in the text are topics to introduce and familiarize the reader with modem design. Topics covered include: microprocessor applications in communications, data modem types, microprocessor and VLSI types, and technological impacts on design. Finally, we address the hardware issues such as the processor elements and interfacing, and software issues like the digital filter implementation. A comprehensive bibliography on modem design and implementation is also provided. With this bibliography one can research VLSI/microprocessor-based data modem design easily and thoroughly

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

The Design and Implementation of the Dynamic Ionosphere Cubesat Experiment (Dice) Science Instruments

Dynamic Ionosphere Cubesat Experiment (DICE) is a satellite project funded by the National Science Foundation (NSF) to study the ionosphere, more particularly Storm Enhanced Densities (SED) with a payload consisting of plasma diagnostic instrumentation. Three instruments onboard DICE include an Electric Field Probe (EFP), Ion Langmuir Probe (ILP), and Three Axis Magnetometer (TAM). The EFP measures electric fields from 8V and consists of three channels a DC to 40Hz channel, a Floating Potential Probe (FPP), and an spectrographic channel with four bands from 16Hz to 512Hz. The ILP measures plasma densities from 1x104 cm-3 to 2x107 cm-3. The TAM measures magnetic field strength with a range 0.5 Gauss with a sensitivity of 2nT. To achieve desired mission requirements careful selection of instrument requirements and planning of the instrumentation design to achieve mission success. The analog design of each instrument is described in addition to the digital framework required to sample the science data at a 70Hz rate and prepare the data for the Command and Data Handing (C&DH) system. Calibration results are also presented and show fulfillment of the mission and instrumentation requirements