Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors

Degradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

Electrical characterization and modelling of lateral DMOS transistor:investigation of capacitances and hot-carrier impact

With the work reported in this manuscript we have essentially contributed to the electrical characterization and modelling of high voltage MOSFETs, more particularly DMOS architectures such as X-DMOS and L-DMOS able to sustain voltages ranging from 30V to 100V. The technology information and the investigated devices have been kindly provided by AMIS, Belgium (former Alcatel Microelectronics). In general, all the initial defined targets in term of the orientation of our work, as defined in the introduction chapter, have been maintained along the progress of the work. However, sometimes, based on the obtained results we have decided to pay more attention to some less explored topics such as the hot carrier impact of DMOS capacitances and the combined effect of stress and temperature, which initially were not among the planned activities. However, we believe that we have contributed to some of the planned targets. We experimentally validated the concept of intrinsic drain voltage; a modeling concept dedicated to the modeling of HV MOSFET and demonstrated its usefulness for the DC and AC modelling of HV devices. We proposed an original mathematical yet quasi-empirical formulation for the bias-dependent drift series resistance of DMOS transistor, which is very accurate for modelling all the regimes of operation of the high voltage device. We combined for the first time such a model with EKV low voltage MOSFET model developed at EPFL. We also have reported on models for the capacitances of high voltage devices at two levels: equivalent circuits for small signal operation based on VK-concept and large signal charge-based models. These models capture the main physical charge distribution in the device but they are less adapted for fast circuit simulation. In the field of device reliability, we have originally contributed to the investigation of hot carrier effects on DC and AC characteristics of DMOS transistors, with key emphasis on the degradation of transistor capacitances and the influence of the temperature. At our knowledge, our work reported in this chapter is among the first reports existing in this field. We have essentially shown that the monitoring of capacitance degradation if mandatory for a deep understanding of the degradation mechanisms and, in conjunction with DC parameter degradation, could offer correct insights for reliability issues. Even more, we have shown situations (by comparing two fundamental types of stresses) when the capacitance degradation method by HC is much more sensitive than DC parameter degradation method. Of course, some of the combined stress-temperature investigations were too complex to find very coherent explications for all the observed effects but our work stress out the interest and significance of such an approach for defining the SOA of high voltage devices, in general. Overall, our work can be considered as placed at the interface between electrical characterization and modelling of high voltage devices emerging from conventional low voltage CMOS technology, continuing the research tradition in the field established at the Electronics laboratory (LEG) of EPF Lausanne

Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

O impacto dos efeitos da memória de longo termo na linearizabilidade de amplificadores de potência baseados em AlGaN/GaN HEMT

AlGaN/GaN High Electron Mobility Transistor (HEMT)s are among the preferred options for radio-frequency power amplification in cellular base station transmitters and radar applications. However, despite their promising outlook, the pervasiveness of trapping effects makes them resilient to conventional digital predistortion schemes, which not only decrease their current range of applications but could also preclude their integration in future small cells and multiple-input multiple-output architectures where simpler predistortion schemes are mandatory. So, this PhD thesis aims at developing a meaningful link between the device physics and the linearizability of the AlGaN/GaN HEMT-based Power Amplifier (PA). In order to bridge this gap, this thesis begins with a clear explanation for the mechanisms governing the dominant source of trapping effects in standard AlGaN/GaN HEMTs, namely buffer traps. Based on this knowledge, we explain why the best known physically-supported trapping models, used to represent these devices, are insufficient and present a possible improvement to what we consider to be the most accurate model, supported by Technology Computer-Aided Design (TCAD) simulations. This has also been corroborated through a novel double-pulse technique able to describe experimentally both the capture and emission transients in a wide temporal span under guaranteed isothermal conditions. The measured stretched capture transients validated our understanding of the process while the temperature dependence of the emission profiles confirmed buffer traps as the dominant source of trapping effects. Finally, through both simulations and experimental results, we elaborate here the relationship between the emission time constant and the achievable linearity of GaN HEMT-based PAs, showing that the worst-case scenario happens when the emission time constant is on the order of the time between consecutive envelope peaks above a certain amplitude threshold. This is the case in which we observed a more pronounced hysteresis on the gain and phase-shift characteristics, and so, a stronger impact of the memory effects. The main outcome of this thesis suggests that the biggest linearizability concern in standard AlGaN/GaN HEMT-based PAs lies on the large emission time constants of buffer traps.AlGaN/GaN HEMTs estão entre as opções preferidas para amplificação de potência de radiofrequência em transmissores de estacão base celular e aplicações de radar. No entanto, apesar de sua perspetiva promissora, a influência dos efeitos de defeitos com níveis profundos torna-os imunes aos esquemas convencionais de pre-distorção digital. Assim, esta tese de doutoramento visa desenvolver uma ligação significativa entre a física do dispositivo e a linearização de amplificadores de potência baseados em Al- GaN/GaN HEMTs. Por forma a preencher esta lacuna, esta tese começa com uma explicação clara dos mecanismos que governam a fonte dominante de efeitos de defeitos com níveis profundos em AlGaN/GaN HEMTs standard, especificamente defeitos no buffer. Com base neste conhecimento, são aparentadas as falhas dos modelos físicos mais conhecidos de defeitos de nível profundo usados para representar estes dispositivos, assim como uma possível melhoria suportada em simulações de TCAD. Isto é também corroborado por uma nova técnica de duplo-pulso capaz de descrever experimentalmente os transientes de captura e emissão num amplo intervalo temporal sob condições isotérmicas. Os transientes de captura medidos validam a nossa compreensão do processo, enquanto que a dependência da temperatura nos perfis de emissão confirmou os defeitos no buffer como a fonte dominante de efeitos de defeitos com níveis profundos. Por fim, através de simulações e resultados experimentais, elabora-se aqui a relação entre a constante de tempo de emissão e a linearizabilidade dos amplificadores baseados em AlGaN/GaN HEMT, mostrando que o pior cenário acontece quando a constante de tempo de emissão é da mesma ordem do tempo entre picos consecutivos da envolvente acima de um certo limiar de amplitude. Este é o caso para o qual se observa uma histerese mais pronunciada nas características de ganho e fase e, consequentemente, um impacto mais forte dos efeitos de memória. O resultado principal desta tese sugere que a maior preocupação na linearização de amplificadores baseados em AlGaN/GaN HEMTs standard está nas grandes constantes de tempo de emissão dos defeitos no buffer.Programa Doutoral em Engenharia Eletrotécnic

Power electronics based on wide-bandgap semiconductors: opportunities and challenges

The expansion of the electric vehicle market is driving the request for efficient and reliable power electronic systems for electric energy conversion and processing. The efficiency, size, and cost of a power system is strongly related to the performance of power semiconductor devices, where massive industrial investments and intense research efforts are being devoted to new wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN). The electrical and thermal properties of SiC and GaN enable the fabrication of semiconductor power devices with performance well beyond the limits of silicon. However, a massive migration of the power electronics industry towards WBG materials can be obtained only once the corresponding fabrication technology reaches a sufficient maturity and a competitive cost. In this paper, we present a perspective of power electronics based on WBG semiconductors, from fundamental material characteristics of SiC and GaN to their potential impacts on the power semiconductor device market. Some application cases are also presented, with specific benchmarks against a corresponding implementation realized with silicon devices, focusing on both achievable performance and system cost

Particle-Based Modeling of Reliability for Millimeter-Wave GaN Devices for Power Amplifier Applications

abstract: In this work, an advanced simulation study of reliability in millimeter-wave (mm-wave) GaN Devices for power amplifier (PA) applications is performed by means of a particle-based full band Cellular Monte Carlo device simulator (CMC). The goal of the study is to obtain a systematic characterization of the performance of GaN devices operating in DC, small signal AC and large-signal radio-frequency (RF) conditions emphasizing on the microscopic properties that correlate to degradation of device performance such as generation of hot carriers, presence of material defects and self-heating effects. First, a review of concepts concerning GaN technology, devices, reliability mechanisms and PA design is presented in chapter 2. Then, in chapter 3 a study of non-idealities of AlGaN/GaN heterojunction diodes is performed, demonstrating that mole fraction variations and the presence of unintentional Schottky contacts are the main limiting factor for high current drive of the devices under study. Chapter 4 consists in a study of hot electron generation in GaN HEMTs, in terms of the accurate simulation of the electron energy distribution function (EDF) obtained under DC and RF operation, taking into account frequency and temperature variations. The calculated EDFs suggest that Class AB PAs operating at low frequency (10 GHz) are more robust to hot carrier effects than when operating under DC or high frequency RF (up to 40 GHz). Also, operation under Class A yields higher EDFs than Class AB indicating lower reliability. This study is followed in chapter 5 by the proposal of a novel π-Shaped gate contact for GaN HEMTs which effectively reduces the hot electron generation while preserving device performance. Finally, in chapter 6 the electro-thermal characterization of GaN-on-Si HEMTs is performed by means of an expanded CMC framework, where charge and heat transport are self-consistently coupled. After the electro-thermal model is validated to experimental data, the assessment of self-heating under lateral scaling is considered.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Diamond Schottky barrier diodes

Research on wide band gap semiconductors suitable for power electronic devices has spread rapidly in the last decade. The remarkable results exhibited by silicon carbide (SiC) Schottky batTier diodes (SBDs), commercially available since 2001, showed the potential of wide band gap semiconductors for replacing silicon (Si) in the range of medium to high voltage applications, where high frequency operation is required. With superior physical and electrical properties, diamond became a potential competitor to SiC soon after Element Six reported in 2002 the successful synthesis of single crystal plasma deposited diamond with high catTier mobility. This thesis discusses the remarkable properties of diamond and introduces several device structures suitable for power electronics. The calculation of several figures of merit emphasize the advantages of diamond with respect to silicon and other wide band gap semiconductors and clearly identifies the areas where its impact would be most significant. Information regarding the first synthesis of diamond, which took place back in 1954, together with data regarding the modern technological process which leads nowadays to high-quality diamond crystals suitable for electronic devices, are reviewed. Models regarding the incomplete ionization of atomic dopants and the variation of catTier mobility with doping level and temperature have been elaborated and included in numerical simulators. The study introduces the novel diamond M-i-P Schottky diode, a version of power Schottky diode which takes advantage of the extremely high intrinsic hole mobility. The structure overcomes the drawback induced by the high activation energies of acceptor dopants in diamond which yield poor hole concentration at room temperature. The complex shape of the on-state characteristic exhibited by diamond M-i-P Schottky structures is thoroughly investigated by means of experimental results, numerical simulations and theoretical considerations. The fabrication of a ramp oxide termination on a diamond device is for the first time reported in this thesis. Both experimental and simulated results show the potential of this termination structure, previously built on Si and SiC power devices. A comprehensive comparison between the ramp oxide and two other versions of the field plate termination concept, the single step and the three-step structures, has been performed, considering aspects such as electrical performance, occupied area, complexity of technological process and cost. Based on experimental results presented in this study, together with predictions made via simulations and theoretical models, it is concluded that diamond M-i-P Schottky diodes have the ability to deliver significantly higher performance compared to that of SiC SBDs if issues such as material defects, Schottky contact formation and measurement of reliable ionization coefficients are carefully addressed in the near future