Generalization of Linear Rosenstark Method of Feedback Amplifier Analysis to Nonlinear One

This paper deals with an extension of the Rosenstark’s linear model of an amplifier to a nonlinear one for the purpose of performing nonlinear distortion analysis. Contrary to an approach using phasors, our method uses the Volterra series. Relying upon the linear model mentioned above, we define first a set of the so-called amplifier’s constitutive equations in an operator form. Then, we expand operators using the Volterra series truncated to the first three components. This leads to getting two representations in the time domain, called in-network and inputoutput type descriptions of an amplifier. Afterwards, both of these representations are transferred into the multi-frequency domains. Their usefulness in calculations of any nonlinear distortion measure as, for example, harmonic, intermodulation, and/or cross-modulation distortion is demonstrated. Moreover, we show that they allow a simple calculation of the so-called nonlinear transfer functions in any topology as, for example, of cascade and feedback structures and their combinations occurring in single-, two-, and three-stage amplifiers. Examples of such calculations are given. Finally in this paper, we comment on usage of such notions as nonlinear signals, intermodulation nonlinearity, and on identification of transfer function poles and zeros lying on the frequency axis with related real-valued frequencies

On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.Comisión Interministerial de Ciencia y Tecnología ME87-000

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Basics of RF electronics

RF electronics deals with the generation, acquisition and manipulation of high-frequency signals. In particle accelerators signals of this kind are abundant, especially in the RF and beam diagnostics systems. In modern machines the complexity of the electronics assemblies dedicated to RF manipulation, beam diagnostics, and feedbacks is continuously increasing, following the demands for improvement of accelerator performance. However, these systems, and in particular their front-ends and back-ends, still rely on well-established basic hardware components and techniques, while down-converted and acquired signals are digitally processed exploiting the rapidly growing computational capability offered by the available technology. This lecture reviews the operational principles of the basic building blocks used for the treatment of high-frequency signals. Devices such as mixers, phase and amplitude detectors, modulators, filters, switches, directional couplers, oscillators, amplifiers, attenuators, and others are described in terms of equivalent circuits, scattering matrices, transfer functions; typical performance of commercially available models is presented. Owing to the breadth of the subject, this review is necessarily synthetic and non-exhaustive. Readers interested in the architecture of complete systems making use of the described components and devoted to generation and manipulation of the signals driving RF power plants and cavities may refer to the CAS lectures on Low-Level RF.Comment: 36 pages, contribution to the CAS - CERN Accelerator School: Specialised Course on RF for Accelerators; 8 - 17 Jun 2010, Ebeltoft, Denmar

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

Use of Phasors in Nonlinear Analysis

In this paper, the well-known method of phasor analysis of linear ac circuits is extended in a rigorous mathematical way to nonlinear analysis. This fills the lack of such a theory in the literature. The results derived enable carrying out the needed corrections of some results published recently that regard harmonic distortion analysis of weakly nonlinear circuits

Novel active function blocks and their applications in frequency filters and quadrature oscillators

Kmitočtové filtry a sinusoidní oscilátory jsou lineární elektronické obvody, které jsou používány v široké oblasti elektroniky a jsou základními stavebními bloky v analogovém zpracování signálu. V poslední dekádě pro tento účel bylo prezentováno velké množství stavebních funkčních bloků. V letech 2000 a 2006 na Ústavu telekomunikací, VUT v Brně byly definovány univerzální proudový konvejor (UCC) a univerzální napět'ový konvejor (UVC) a vyrobeny ve spolupráci s firmou AMI Semiconductor Czech, Ltd. Ovšem, stále existuje požadavek na vývoj nových aktivních prvků, které nabízejí nové výhody. Hlavní přínos práce proto spočívá v definici dalších původních aktivních stavebních bloků jako jsou differential-input buffered and transconductance amplifier (DBTA), current follower transconductance amplifier (CFTA), z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), generalized current follower differential input transconductance amplifier (GCFDITA), voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), a minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Pomocí navržených aktivních stavebních bloků byly prezentovány původní zapojení fázovacích článků prvního řádu, univerzální filtry druhého řádu, ekvivalenty obvodu typu KHN, inverzní filtry, aktivní simulátory uzemněného induktoru a kvadraturní sinusoidní oscilátory pracující v proudovém, napět'ovém a smíšeném módu. Chování navržených obvodů byla ověřena simulací v prostředí SPICE a ve vybraných případech experimentálním měřením.Frequency filters and sinusoidal oscillators are linear electric circuits that are used in wide area of electronics and also are the basic building blocks in analogue signal processing. In the last decade, huge number of active building blocks (ABBs) were presented for this purpose. In 2000 and 2006, the universal current conveyor (UCC) and the universal voltage conveyor (UVC), respectively, were designed at the Department of Telecommunication, BUT, Brno, and produced in cooperation with AMI Semiconductor Czech, Ltd. There is still the need to develop new active elements that offer new advantages. The main contribution of this thesis is, therefore, the definition of other novel ABBs such as the differential-input buffered and transconductance amplifier (DBTA), the current follower transconductance amplifier (CFTA), the z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), the generalized current follower differential input transconductance amplifier (GCFDITA), the voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), and the minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Using the proposed ABBs, novel structures of first-order all-pass filters, second-order universal filters, KHN-equivalent circuits, inverse filters, active grounded inductance simulators, and quadrature sinusoidal oscillators working in the current-, voltage-, or mixed-mode are presented. The behavior of the proposed circuits has been verified by SPICE simulations and in selected cases also by experimental measurements.

RF techniques for IEEE 802.15.4: circuit design and device modelling

The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development

Analogue filter networks: developments in theory, design and analyses

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Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB