Two dimensional analytical threshold voltage modeling of dual material gate S-SOI mosfet

MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is the one of the most important and widely used semiconductor devices used in industry for various proposes. Two most important advantages of MOSFETs are their extremely low power dissipation and small area required for fabrication, i.e high packing density .With the advance of technology the feature sizes of MOSFETs are reduced continuously to increase the packing density of very large scale integration (VLSI) circuits. With continuous shrinkage of device geometrics on threshold voltage causes strong deviations from long channel behavior. The effect of such decrease in channel length is called SCE (Short channel Effect). A two dimensional Poisson equation needs to be solved in order to understand the effect of SCE.SCE (Short Channel Effect) is the effect of reduction in the channel length of MOSFET which results in significant differences from ideal characteristic like channel length modulation, carrier velocity saturation, two dimensional charge sharing, drain induced barrier lowering (DIBL), drain source series resistance and punch through. In order to minimize the effect of short channel effect various different modeling has been introduced. Among them DG MOSFET (Double Gate MOSFET), SOI MOSFET (Silicon-On Insulator MOSFET) are particularly important. In this thesis, a two dimensional threshold voltage model is developed for a Dual Material Gate Fully Depleted Strained Silicon on Insulator (DMG-FD-S-SOI) MOSFET considering the interface trap charges. The interface trap charges during the pre and post fabrication process are a common phenomenon, and these charges can’t be neglected in nano scale devices. For finding out the surface potential, parabolic approximation is utilized to solve 2D Poisson’s equation in the channel region. Further, the virtual cathode potential method is used to formulate the threshold voltage

An equivalent circuit model of the traveling wave electrode for carrier-depletion-based silicon optical modulators

We propose an equivalent circuit model for the coplanar waveguide (CPW) which serves as the traveling wave electrode to drive carrier-depletion-based silicon modulators. Conformal mapping and partial capacitance techniques are employed to calculate each element of the circuit. The validity of the model is confirmed by the comparison with both finite-element simulation and experimental result. With the model, we calculate the modulation bandwidth for different CPW dimensions and termination impedances. A 3 dB modulation bandwidth of 15 GHz is demonstrated with a traveling wave electrode of 3 mm. The calculation indicates that, by utilizing a traveling wave electrode of 2 mm, we can obtain a 3 dB modulation bandwidth of 28 GHz

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (leaves 85-91).Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the channel. In bulk-like devices, the device designer keeps the gate in control with gate oxide scaling and doping profile design. In thin-body geometries, silicon thickness is a new, powerful scaling parameter. Much like with gate oxide scaling, the electrostatics improve with thinner films. This means that the limits of scaling thin-body devices are closely tied with the limits of scaling silicon film thickness. Electrical transport appears to be one of the limiting factors for scaling body thickness. As the silicon film thickness is reduced into the ultra-thin regime, where the film is thinner than the bulk inversion layer thickness, quantum confinement effects begin to be observed. For the most part, these effects act to degrade mobility, reducing performance and making further scaling less rewarding. This work focuses on finding methods to maintain good mobility in ultra-thin silicon films. Thin and ultra-thin body relaxed SOI and biaxially strained SOI MOSFETs were constructed and measured with and without the application of mechanical uniaxial strain to examine the interaction between strain and thin-film effects.(cont.) The band splitting induced by the application of strain is found to at least partially mitigate the mechanisms responsible for degrading electron mobility in ultra-thin films. Additionally, the enhancement seen with uniaxial strain is found to further enhance mobility in biaxially strained films. Finally, the effective mass change caused by uniaxial strain is found to cause the mobility modulation to have a directional dependence, especially in already biaxially strained films.by Isaac Lauer.Ph.D

Analytical Modeling of Nanoscale 4H-SiC MOSFETs for High Power Applications

Threshold voltage instability was investigated for 4H-SiC MOSFETs with SiO2, Si3N4 and HFO2 gate oxides. Threshold voltage changes observed in the drain current Vs. gate voltage (ID-VG) characteristics was determined using various gate voltage sweeps at room temperature. Three types of MOSFETs show different instability characteristics. Depending on gate voltage, many difficulties come up with 4H-SiC MOSFETs, such as low mobility and poor reliability. The characteristics like channel potential, field distribution and the threshold voltage of the proposed models of MOSFETs, 4H-SiC and SOI-4H-SiC were compared with simulator results to validate the models. Short channel effects (SCEs) were also investigated and compared with the existing nanoscale silicon MOSFETs The surface potential model is calculated by using the two-dimensional Poisson equation. The specification of the model are examined by several MOSFET parameters such as body doping concentration, metal gate work function, silicon carbide layer thickness, thickness of metal gate oxide layer, buried oxide thickness, drain to source voltage, and gate to source voltage. The outcomes of modeling and simulation of 4H-SiC MOSFETs model show that the proposed models can reduce short channel effects more than the Silicon MOSFETs. Proposed models highly reduces the drain-induced-barrier-lowering (DIBL) to meet the performance fullfilmant in Nano electronic applications when compared to silicon MOSFETs. Establishing the results, we have noticed that this model can be utilized as a useful tool for the characterization and design of high-efficiency 4H-SiC nanoscale MOSFETs. By matching the two-dimensional device simulation results with analytical modeling, the validity of the recommended models are proven

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

As the silicon CMOS technology move into the sub-20nm regime, manufacturing limits and fundamental curb the traditional scaling of transistors. Modernization in device structures and materials will be needed for continued transistor miniaturization and equivalent performance improvements. Device dimensions are approaching their scaling limit giving rise to undesirable effects like short channel effects, gate leakage current, drain induced barrier lowering (DIBL) etc. Strained-silicon devices have been receiving enormous attention owing to their potential for achieving higher channel mobility and drive current enhancement and compatibility with conventional silicon processing.In this novel work, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon ( ) on silicon-germanium ( ) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations and also, the sub threshold swing is also analyzed for the device with different parameter variation. The model is used to investigate the excellent immunity against SCE offered by the DMG structure. The validity of the present 2D analytical model is verified with ATLASTM, a 2D device simulator from Silvaco Inc

Modeling & Performance Enhancement Analysis of Some Nanoscale MOSFET Structures

Silicon-on-Insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications. Recent experimental studies invigorated interest in Fully Depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Various new structures with different engineering concepts have been reported to reduce the SCEs in SOI platform. Among them Strain engineering and high-k gate dielectric with metal gate technology are very popular for enhancing the carrier mobility and reduction of gate leakage current. In this thesis, first physics based 2-D model for surface potential, threshold voltage and electric field for a Fully Depleted Strained Silicon on Insulator (FD-S-SOI) MOSFET by solving the two dimensional Poisson’s equation is presented. The model details the role of various MOS parameters like germanium concentration, body doping concentration, strained silicon thickness, oxide thickness and gate metal work function influencing the surface potential, threshold voltage and electric field. Then extensive numerical simulation is done to study the effect of device design engineering on the analog/RF performance of nanoscale DGMOSFET by varying the gate work function, channel length and gate oxide. Including the Short Channel Effects (SCEs) the important analog/RF figures of merit (FOMs) are also examined. Finally one optimum device is presented with great immunization to SCEs and highly applicable to analog/RF applications