5,697 research outputs found
Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation
A novel approach to hardware fault tolerance is demonstrated that takes inspiration from the human immune system as a method of fault detection. The human immune system is a remarkable system of interacting cells and organs that protect the body from invasion and maintains reliable operation even in the presence of invading bacteria or viruses. This paper seeks to address the field of electronic hardware fault tolerance from an immunological perspective with the aim of showing how novel methods based upon the operation of the immune system can both complement and create new approaches to the development of fault detection mechanisms for reliable hardware systems. In particular, it is shown that by use of partial matching, as prevalent in biological systems, high fault coverage can be achieved with the added advantage of reducing memory requirements. The development of a generic finite-state-machine immunization procedure is discussed that allows any system that can be represented in such a manner to be "immunized" against the occurrence of faulty operation. This is demonstrated by the creation of an immunized decade counter that can detect the presence of faults in real tim
Submicron Systems Architecture Project: Semiannual Technical Report
No abstract available
Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures
abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies.
Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques.
A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Built-In Self-Test (BIST) for Multi-Threshold NULL Convention Logic (MTNCL) Circuits
This dissertation proposes a Built-In Self-Test (BIST) hardware implementation for Multi-Threshold NULL Convention Logic (MTNCL) circuits. Two different methods are proposed: an area-optimized topology that requires minimal area overhead, and a test-performance-optimized topology that utilizes parallelism and internal hardware to reduce the overall test time through additional controllability points. Furthermore, an automated software flow is proposed to insert, simulate, and analyze an input MTNCL netlist to obtain a desired fault coverage, if possible, through iterative digital and fault simulations. The proposed automated flow is capable of producing both area-optimized and test-performance-optimized BIST circuits and scripts for digital and fault simulation using commercial software that may be utilized to manually verify or adjust further, if desired
Advanced flight control system study
A fly by wire flight control system architecture designed for high reliability includes spare sensor and computer elements to permit safe dispatch with failed elements, thereby reducing unscheduled maintenance. A methodology capable of demonstrating that the architecture does achieve the predicted performance characteristics consists of a hierarchy of activities ranging from analytical calculations of system reliability and formal methods of software verification to iron bird testing followed by flight evaluation. Interfacing this architecture to the Lockheed S-3A aircraft for flight test is discussed. This testbed vehicle can be expanded to support flight experiments in advanced aerodynamics, electromechanical actuators, secondary power systems, flight management, new displays, and air traffic control concepts
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
Abstract-Asynchronous controllers exhibit various characteristics that limit the effectiveness and applicability of the Concurrent Error Detection (CED) methods developed for their synchronous counterparts. Asynchronous Burst-Mode Machines (ABMMs), for example, do not have a global clock to synchronize the ABMM with the additional circuitry that is typically used by synchronous CED methods (for example, duplication). Therefore, performing effective CED in ABMMs requires a synchronization method that will appropriately enable the checker (for example, comparator) in order to avoid false alarms. Also, ABMMs contain redundant logic, which guarantees the hazard-free operation required for correct interaction between the circuit and its environment. Redundant logic, however, allows some single event transients to manifest themselves only as hazards but not as logic discrepancies. Therefore, performing effective CED in ABMMs requires the ability to detect hazards with which synchronous CED methods are not concerned. In this work, we first devise hardware solutions for performing checking synchronization and hazard detection. We then demonstrate how these solutions enable the development of three complete CED methods for ABMMs. The first method (Duplication-based CED) is an adaptation of the well-known duplication method within the context of ABMMs. The second method (Transition-Triggered CED) is a variation of duplication wherein the implementation cost is reduced by allowing hazards in the duplicate circuit. In contrast to these two methods, which are nonintrusive, the third method (Berger code-based CED) is intrusive since it requires reencoding of the ABMM with check symbols based on the Berger code. Although this intrusiveness may slightly impact performance, Berger code-based CED incurs the lowest area overhead among the three methods, as indicated through experimental results
Reversible Computation: Extending Horizons of Computing
This open access State-of-the-Art Survey presents the main recent scientific outcomes in the area of reversible computation, focusing on those that have emerged during COST Action IC1405 "Reversible Computation - Extending Horizons of Computing", a European research network that operated from May 2015 to April 2019. Reversible computation is a new paradigm that extends the traditional forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as easily and naturally as forwards. It aims to deliver novel computing devices and software, and to enhance existing systems by equipping them with reversibility. There are many potential applications of reversible computation, including languages and software tools for reliable and recovery-oriented distributed systems and revolutionary reversible logic gates and circuits, but they can only be realized and have lasting effect if conceptual and firm theoretical foundations are established first
Techniques for the realization of ultra- reliable spaceborne computer Final report
Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer
Transient error mitigation by means of approximate logic circuits
Mención Internacional en el título de doctorThe technological advances in the manufacturing of electronic circuits have allowed to
greatly improve their performance, but they have also increased the sensitivity of electronic
devices to radiation-induced errors. Among them, the most common effects are
the SEEs, i.e., electrical perturbations provoked by the strike of high-energy particles,
which may modify the internal state of a memory element (SEU) or generate erroneous
transient pulses (SET), among other effects. These events pose a threat for the reliability
of electronic circuits, and therefore fault-tolerance techniques must be applied to
deal with them.
The most common fault-tolerance techniques are based in full replication (DWC or
TMR). These techniques are able to cover a wide range of failure mechanisms present
in electronic circuits. However, they suffer from high overheads in terms of area and
power consumption. For this reason, lighter alternatives are often sought at the expense
of slightly reducing reliability for the least critical circuit sections. In this context a new
paradigm of electronic design is emerging, known as approximate computing, which
is based on improving the circuit performance in change of slight modifications of the
intended functionality. This is an interesting approach for the design of lightweight
fault-tolerant solutions, which has not been yet studied in depth.
The main goal of this thesis consists in developing new lightweight fault-tolerant
techniques with partial replication, by means of approximate logic circuits. These
circuits can be designed with great flexibility. This way, the level of protection as
well as the overheads can be adjusted at will depending on the necessities of each
application. However, finding optimal approximate circuits for a given application is
still a challenge.
In this thesis a method for approximate circuit generation is proposed, denoted
as fault approximation, which consists in assigning constant logic values to specific
circuit lines. On the other hand, several criteria are developed to generate the most
suitable approximate circuits for each application, by using this fault approximation
mechanism. These criteria are based on the idea of approximating the least testable
sections of circuits, which allows reducing overheads while minimising the loss of reliability.
Therefore, in this thesis the selection of approximations is linked to testability
measures.
The first criterion for fault selection developed in this thesis uses static testability
measures. The approximations are generated from the results of a fault simulation of
the target circuit, and from a user-specified testability threshold. The amount of approximated
faults depends on the chosen threshold, which allows to generate approximate circuits with different performances. Although this approach was initially intended for
combinational circuits, an extension to sequential circuits has been performed as well,
by considering the flip-flops as both inputs and outputs of the combinational part of
the circuit. The experimental results show that this technique achieves a wide scalability,
and an acceptable trade-off between reliability versus overheads. In addition, its
computational complexity is very low.
However, the selection criterion based in static testability measures has some drawbacks.
Adjusting the performance of the generated approximate circuits by means of
the approximation threshold is not intuitive, and the static testability measures do not
take into account the changes as long as faults are approximated. Therefore, an alternative
criterion is proposed, which is based on dynamic testability measures. With this
criterion, the testability of each fault is computed by means of an implication-based
probability analysis. The probabilities are updated with each new approximated fault,
in such a way that on each iteration the most beneficial approximation is chosen, that
is, the fault with the lowest probability. In addition, the computed probabilities allow
to estimate the level of protection against faults that the generated approximate circuits
provide. Therefore, it is possible to generate circuits which stick to a target error rate.
By modifying this target, circuits with different performances can be obtained. The
experimental results show that this new approach is able to stick to the target error rate
with reasonably good precision. In addition, the approximate circuits generated with
this technique show better performance than with the approach based in static testability
measures. In addition, the fault implications have been reused too in order to
implement a new type of logic transformation, which consists in substituting functionally
similar nodes.
Once the fault selection criteria have been developed, they are applied to different
scenarios. First, an extension of the proposed techniques to FPGAs is performed,
taking into account the particularities of this kind of circuits. This approach has been
validated by means of radiation experiments, which show that a partial replication with
approximate circuits can be even more robust than a full replication approach, because
a smaller area reduces the probability of SEE occurrence. Besides, the proposed
techniques have been applied to a real application circuit as well, in particular to the
microprocessor ARM Cortex M0. A set of software benchmarks is used to generate
the required testability measures. Finally, a comparative study of the proposed approaches
with approximate circuit generation by means of evolutive techniques have
been performed. These approaches make use of a high computational capacity to generate
multiple circuits by trial-and-error, thus reducing the possibility of falling into
local minima. The experimental results demonstrate that the circuits generated with
evolutive approaches are slightly better in performance than the circuits generated with
the techniques here proposed, although with a much higher computational effort.
In summary, several original fault mitigation techniques with approximate logic
circuits are proposed. These approaches are demonstrated in various scenarios, showing
that the scalability and adaptability to the requirements of each application are their
main virtuesLos avances tecnológicos en la fabricación de circuitos electrónicos han permitido mejorar
en gran medida sus prestaciones, pero también han incrementado la sensibilidad
de los mismos a los errores provocados por la radiación. Entre ellos, los más comunes
son los SEEs, perturbaciones eléctricas causadas por el impacto de partículas de alta
energía, que entre otros efectos pueden modificar el estado de los elementos de memoria
(SEU) o generar pulsos transitorios de valor erróneo (SET). Estos eventos suponen
un riesgo para la fiabilidad de los circuitos electrónicos, por lo que deben ser tratados
mediante técnicas de tolerancia a fallos.
Las técnicas de tolerancia a fallos más comunes se basan en la replicación completa
del circuito (DWC o TMR). Estas técnicas son capaces de cubrir una amplia variedad
de modos de fallo presentes en los circuitos electrónicos. Sin embargo, presentan un
elevado sobrecoste en área y consumo. Por ello, a menudo se buscan alternativas más
ligeras, aunque no tan efectivas, basadas en una replicación parcial. En este contexto
surge una nueva filosofía de diseño electrónico, conocida como computación aproximada,
basada en mejorar las prestaciones de un diseño a cambio de ligeras modificaciones
de la funcionalidad prevista. Es un enfoque atractivo y poco explorado para el diseño
de soluciones ligeras de tolerancia a fallos.
El objetivo de esta tesis consiste en desarrollar nuevas técnicas ligeras de tolerancia
a fallos por replicación parcial, mediante el uso de circuitos lógicos aproximados. Estos
circuitos se pueden diseñar con una gran flexibilidad. De este forma, tanto el nivel de
protección como el sobrecoste se pueden regular libremente en función de los requisitos
de cada aplicación. Sin embargo, encontrar los circuitos aproximados óptimos para
cada aplicación es actualmente un reto.
En la presente tesis se propone un método para generar circuitos aproximados, denominado
aproximación de fallos, consistente en asignar constantes lógicas a ciertas
líneas del circuito. Por otro lado, se desarrollan varios criterios de selección para, mediante
este mecanismo, generar los circuitos aproximados más adecuados para cada
aplicación. Estos criterios se basan en la idea de aproximar las secciones menos testables
del circuito, lo que permite reducir los sobrecostes minimizando la perdida de
fiabilidad. Por tanto, en esta tesis la selección de aproximaciones se realiza a partir de
medidas de testabilidad.
El primer criterio de selección de fallos desarrollado en la presente tesis hace uso de
medidas de testabilidad estáticas. Las aproximaciones se generan a partir de los resultados
de una simulación de fallos del circuito objetivo, y de un umbral de testabilidad
especificado por el usuario. La cantidad de fallos aproximados depende del umbral escogido, lo que permite generar circuitos aproximados con diferentes prestaciones.
Aunque inicialmente este método ha sido concebido para circuitos combinacionales,
también se ha realizado una extensión a circuitos secuenciales, considerando los biestables
como entradas y salidas de la parte combinacional del circuito. Los resultados
experimentales demuestran que esta técnica consigue una buena escalabilidad, y unas
prestaciones de coste frente a fiabilidad aceptables. Además, tiene un coste computacional
muy bajo.
Sin embargo, el criterio de selección basado en medidas estáticas presenta algunos
inconvenientes. No resulta intuitivo ajustar las prestaciones de los circuitos aproximados
a partir de un umbral de testabilidad, y las medidas estáticas no tienen en cuenta los
cambios producidos a medida que se van aproximando fallos. Por ello, se propone un
criterio alternativo de selección de fallos, basado en medidas de testabilidad dinámicas.
Con este criterio, la testabilidad de cada fallo se calcula mediante un análisis de probabilidades
basado en implicaciones. Las probabilidades se actualizan con cada nuevo
fallo aproximado, de forma que en cada iteración se elige la aproximación más favorable,
es decir, el fallo con menor probabilidad. Además, las probabilidades calculadas
permiten estimar la protección frente a fallos que ofrecen los circuitos aproximados
generados, por lo que es posible generar circuitos que se ajusten a una tasa de fallos
objetivo. Modificando esta tasa se obtienen circuitos aproximados con diferentes prestaciones.
Los resultados experimentales muestran que este método es capaz de ajustarse
razonablemente bien a la tasa de fallos objetivo. Además, los circuitos generados
con esta técnica muestran mejores prestaciones que con el método basado en medidas
estáticas. También se han aprovechado las implicaciones de fallos para implementar
un nuevo tipo de transformación lógica, consistente en sustituir nodos funcionalmente
similares.
Una vez desarrollados los criterios de selección de fallos, se aplican a distintos
campos. En primer lugar, se hace una extensión de las técnicas propuestas para FPGAs,
teniendo en cuenta las particularidades de este tipo de circuitos. Esta técnica se ha validado
mediante experimentos de radiación, los cuales demuestran que una replicación
parcial con circuitos aproximados puede ser incluso más robusta que una replicación
completa, ya que un área más pequeña reduce la probabilidad de SEEs. Por otro lado,
también se han aplicado las técnicas propuestas en esta tesis a un circuito de aplicación
real, el microprocesador ARM Cortex M0, utilizando un conjunto de benchmarks
software para generar las medidas de testabilidad necesarias. Por ´último, se realiza un
estudio comparativo de las técnicas desarrolladas con la generación de circuitos aproximados
mediante técnicas evolutivas. Estas técnicas hacen uso de una gran capacidad
de cálculo para generar múltiples circuitos mediante ensayo y error, reduciendo la posibilidad
de caer en algún mínimo local. Los resultados confirman que, en efecto, los
circuitos generados mediante técnicas evolutivas son ligeramente mejores en prestaciones
que con las técnicas aquí propuestas, pero con un coste computacional mucho
mayor.
En definitiva, se proponen varias técnicas originales de mitigación de fallos mediante
circuitos aproximados. Se demuestra que estas técnicas tienen diversas aplicaciones,
haciendo de la flexibilidad y adaptabilidad a los requisitos de cada aplicación
sus principales virtudes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Raoul Velazco.- Secretario: Almudena Lindoso Muñoz.- Vocal: Jaume Segura Fuste
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