ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究

本研究は、半導体上に集積されたアナログ・ディジタル・メモリ回路から構成されるミクストシグナルシステムを別の製造プロセスへ移行することをポーティングとして定義し、効率的なポーティングを行うための設計方式と自動回路合成アルゴリズムを提案し、いくつかの典型的な回路に対する設計事例を示し、提案手法の妥当性を立証している。北九州市立大

A test structure for the measurement and characterization of layout-induced transistor variation

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 131-139).Transistor scaling has enabled us to design circuits with higher performance, lower cost, and higher density; billions of transistors can now be integrated onto a single die. However, this trend also magnifies the significance of device variability. In this thesis, we focus on the study of layout-induced systematic variation. Specifically, we investigate how pattern densities can affect transistor behavior. Two pattern densities are chosen in our design: polysilicon density and shallow-trench isolation (STI) density. A test structure is designed to study the systematic spatial dependency between transistors in order to determine the impact of different variation sources on transistor characteristics and understand the radius of influence that defines the neighborhood of shapes which play a part in determining the transistor characteristics. A more accurate transistor model based on surrounding layout details can be built using these results. The test structure is divided into six blocks, each having a different polysilicon density or STI density. A rapid change of pattern density between blocks is designed to emulate a step response for future modeling. The two pattern densities are chosen to reflect the introduction of new process technologies, such as strain engineering and rapid thermal annealing. The test structure is designed to have more than 260K devices under test (DUT). In addition to the changes in pattern density, the impact of transistor sizing, number of polysilicon fingers, finger spacing, and active area are also explored and studied in this thesis. Two different test circuits are designed to perform the measurement.(cont.) The first test circuit is designed to work with of-chip wafer probe testing equipment; the second test circuit is designed to have on-chip current measurement capabilities using a high dynamic range analog-to-digital converter (ADC). The ADC has a dynamic range of over four orders of magnitude to measure currents from 50nA to 1mA. The test chip also implements a hierarchical design with a minimum amount of peripheral circuitry, so that most of the chip area is dedicated for the transistors under test.by Albert Hsu Ting Chang.S.M

Feasibility of Geiger-mode avalanche photodiodes in CMOS standard technologies for tracker detectors

The next generation of particle colliders will be characterized by linear lepton colliders, where the collisions between electrons and positrons will allow to study in great detail the new particle discovered at CERN in 2012 (presumably the Higgs boson). At present time, there are two alternative projects underway, namely the ILC (International Linear Collider) and CLIC (Compact LInear Collider). From the detector point of view, the physics aims at these particle colliders impose such extreme requirements, that there is no sensor technology available in the market that can fulfill all of them. As a result, several new detector systems are being developed in parallel with the accelerator. This thesis presents the development of a GAPD (Geiger-mode Avalanche PhotoDiode) pixel detector aimed mostly at particle tracking at future linear colliders. GAPDs offer outstanding qualities to meet the challenging requirements of ILC and CLIC, such as an extraordinary high sensitivity, virtually infinite gain and ultra-fast response time, apart from compatibility with standard CMOS technologies. In particular, GAPD detectors enable the direct conversion of a single particle event onto a CMOS digital pulse in the sub-nanosecond time scale without the utilization of either preamplifiers or pulse shapers. As a result, GAPDs can be read out after each single bunch crossing, a unique quality that none of its competitors can offer at the moment. In spite of all these advantages, GAPD detectors suffer from two main problems. On the one side, there exist noise phenomena inherent to the sensor, which induce noise pulses that cannot be distinguished from real particle events and also worsen the detector occupancy to unacceptable levels. On the other side, the fill-factor is too low and gives rise to a reduced detection efficiency. Solutions to the two problems commented that are compliant with the severe specifications of the next generation of particle colliders have been thoroughly investigated. The design and characterization of several single pixels and small arrays that incorporate some elements to reduce the intrinsic noise generated by the sensor are presented. The sensors and the readout circuits have been monolithically integrated in a conventional HV-CMOS 0.35 μm process. Concerning the readout circuits, both voltage-mode and current-mode options have been considered. Moreover, the time-gated operation has also been explored as an alternative to reduce the detected sensor noise. The design and thorough characterization of a prototype GAPD array, also monolithically integrated in a conventional 0.35 μm HV-CMOS process, is presented in the thesis as well. The detector consists of 10 rows x 43 columns of pixels, with a total sensitive area of 1 mm x 1 mm. The array is operated in a time-gated mode and read out sequentially by rows. The efficiency of the proposed technique to reduce the detected noise is shown with a wide variety of measurements. Further improved results are obtained with the reduction of the working temperature. Finally, the suitability of the proposed detector array for particle detection is shown with the results of a beam-test campaign conducted at CERN-SPS (European Organization for Nuclear Research-Super Proton Synchrotron). Apart from that, a series of additional approaches to improve the performance of the GAPD technology are proposed. The benefits of integrating a GAPD pixel array in a 3D process in terms of overcoming the fill-factor limitation are examined first. The design of a GAPD detector in the Global Foundries 130 nm/Tezzaron 3D process is also presented. Moreover, the possibility to obtain better results in light detection applications by means of the time-gated operation or correction techniques is analyzed too.Aquesta tesi presenta el desenvolupament d’un detector de píxels de GAPDs (Geiger-mode Avalanche PhotoDiodes) dedicat principalment a rastrejar partícules en futurs col•lisionadors lineals. Els GAPDs ofereixen unes qualitats extraordinàries per satisfer els requisits extremadament exigents d’ILC (International Linear Collider) i CLIC (Compact LInear Collider), els dos projectes per la propera generació de col•lisionadors que s’han proposat fins a dia d’avui. Entre aquestes qualitats es troben una sensibilitat extremadament elevada, un guany virtualment infinit i una resposta molt ràpida, a part de ser compatibles amb les tecnologies CMOS estàndard. En concret, els detectors de GAPDs fan possible la conversió directa d’un esdeveniment generat per una sola partícula en un senyal CMOS digital amb un temps inferior al nanosegon. Com a resultat d’aquest fet, els GAPDs poden ser llegits després de cada bunch crossing (la col•lisió de les partícules), una qualitat única que cap dels seus competidors pot oferir en el moment actual. Malgrat tots aquests avantatges, els detectors de GAPDs pateixen dos grans problemes. D’una banda, existeixen fenòmens de soroll inherents al sensor, els quals indueixen polsos de soroll que no poden ser distingits dels esdeveniments reals generats per partícules i que a més empitjoren l’ocupació del detector a nivells inacceptables. D’altra banda, el fill-factor (és a dir, l’àrea sensible respecte l’àrea total) és molt baix i redueix l’eficiència detectora. En aquesta tesi s’han investigat solucions als dos problemes comentats i que a més compleixen amb les especificacions altament severes dels futurs col•lisionadors lineals. El detector de píxels de GAPDs, el qual ha estat monolíticament integrat en un procés HV-CMOS estàndard de 0.35 μm, incorpora circuits de lectura en mode voltatge que permeten operar el sensor en l’anomenat mode time-gated per tal de reduir el soroll detectat. L’eficiència de la tècnica proposada queda demostrada amb la gran varietat d’experiments que s’han dut a terme. Els resultats del beam-test dut a terme al CERN indiquen la capacitat del detector de píxels de GAPDs per detectar partícules altament energètiques. A banda d’això, també s’han estudiat els beneficis d’integrar un detector de píxels de GAPDs en un procés 3D per tal d’incrementar el fill-factor. L’anàlisi realitzat conclou que es poden assolir fill-factors superiors al 90%

The Conference on High Temperature Electronics

The status of and directions for high temperature electronics research and development were evaluated. Major objectives were to (1) identify common user needs; (2) put into perspective the directions for future work; and (3) address the problem of bringing to practical fruition the results of these efforts. More than half of the presentations dealt with materials and devices, rather than circuits and systems. Conference session titles and an example of a paper presented in each session are (1) User requirements: High temperature electronics applications in space explorations; (2) Devices: Passive components for high temperature operation; (3) Circuits and systems: Process characteristics and design methods for a 300 degree QUAD or AMP; and (4) Packaging: Presently available energy supply for high temperature environment

NASA Tech Briefs, September 1995

A special focus for this issue is Sensors. Topics covered include : Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Life Sciences; Mechanics; Machinery; Fabrication Technology; and Mathematics and Information Sciences. A section of Laser Tech Briefs is included

SIS 2017. Statistics and Data Science: new challenges, new generations

The 2017 SIS Conference aims to highlight the crucial role of the Statistics in Data Science. In this new domain of ‘meaning’ extracted from the data, the increasing amount of produced and available data in databases, nowadays, has brought new challenges. That involves different fields of statistics, machine learning, information and computer science, optimization, pattern recognition. These afford together a considerable contribute in the analysis of ‘Big data’, open data, relational and complex data, structured and no-structured. The interest is to collect the contributes which provide from the different domains of Statistics, in the high dimensional data quality validation, sampling extraction, dimensional reduction, pattern selection, data modelling, testing hypotheses and confirming conclusions drawn from the data