Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Development of interconnections for mm-wave antenna module package

Abstract. The increase in mobile network data usage has led to interests in mm-wave frequencies (for example 26.5–29.5 GHz) on becoming fifth generation (5G) networks in addition to previously used sub-6 GHz frequencies. The advantage of mm-wave frequencies is larger bandwidth, leading to larger throughput with a tradeoff of smaller coverage due to shorter wavelength. The coverage issue can be compensated by using antenna arrays instead of one antenna. There have been some studies about stacking antenna module package vertically on motherboard, and in more advanced approach, the RFIC is integrated into the bottom of the antenna module package. This thesis concentrates on developing the interconnection between two PWBs on mm-wave frequency (26.5–29.5 GHz) between the antenna module and motherboard. More accurately, creating interconnection around via structure, carrying RF-signal from antenna module to motherboard by applying vertical stacking. This method may reduce the overall price of the system, while increasing the level of integration in the system. The overall aim of this thesis was to provide a functional and optimized interconnection method with measurement results and limitations of Nokia Factory. The interconnection can be created by using electromagnetic coupling or galvanic connection. The galvanic connection was chosen for many reasons and different interconnection methods applying galvanic connection were introduced. These methods include LGA and BGA soldering, traditional RF-connector and antenna array connector with 16-ports. After considering the options and Nokia Factory limitations, the most suitable interconnection method turned out to be LGA soldering. The research work includes partial design of antenna module and motherboard, and the optimization for connection. Prototypes were created based on the design, and the measurement results and conclusions of interconnection functionality were provided as well. Six prototypes were made, from which prototypes 3–6 were functional in terms of solder height. The measurement results show that there was variation in matching between different prototypes and between simulation and measurement results. By doing x-ray and failure analysis, a few reasons were found to explain the variation. One reason can be found from voids in signal soldering, which widens the soldering horizontally, leading to decreased matching due to changed solder diameter and asymmetric grounding. However, by utilizing the solder bumping method, the appearance and diameter of voids can be minimized. The conclusion with prototypes was that the system functions well, but improvements are recommended, and simulations should be re-done with modifications from failure analysis. Overall, the aim of the thesis was reached.Antennimoduulipaketin liitäntöjen kehittäminen millimetriaalto taajuuksille. Tiivistelmä. Datankäytön jatkuvan kasvun takia viidennen sukupolven (5G) matkapuhelinteknologian kehitys on keskittynyt aiemmin käytettyjen alle 6 GHz taajuuksien lisäksi uusille, korkeammille, millimetriaaltojen (esim. 26.5–29.5 GHz) taajuuskaistalle. Korkeammat taajuudet tarjoavat mahdollisuuden käyttää suurempia kaistanleveyksiä kasvattaen läpikulkevan datan määrää, mutta sen hintana on signaalin kantomatkan pienentyminen aallonpituuden pienentymisen takia. Kantomatkan lyhenemistä voidaan kuitenkin kompensoida käyttämällä antenniryhmiä yksittäisten antennien asemasta. Antenniryhmien integroinnista systeemiin on tehty erilaisia tutkimuksia, joita ovat esimerkiksi vertikaalinen pinoaminen, jossa antennilevy juotetaan toiselle piirilevylle. Edistyksellisemmässä versiossa kyseisen antennilevyn pohjaan on liitetty RFIC piiri. Tässä diplomityössä tutkittiin kahden piirilevyn välistä liityntäkohtaa vertikaalisella pinoamisella. Liityntäkohta kuljettaa millimetriaaltotaajuista RF-signaalia (26.5–29.5 GHz) antennilevyltä äitilevylle. Kyseisellä rakenteella voidaan saada pienennettyä mahdollisen tuotteen kustannuksia, samalla pienentäen myös sen fyysistä kokoa. Työn tarkoituksena on tarjota Nokialle valmiiksi optimoitu liitäntäratkaisu mittaustuloksineen ja tuotannon rajoitteineen dokumentoituna. Tutkittu liityntäkohta voidaan muodostaa sähkömagneettisella kytkeytymisellä tai galvaanisesti, joista jälkimmäinen on huomattavasti järkevämpi ja tässä työssä on esitetty sille erilaisia vaihtoehtoja, joita on vertailtu toisiinsa. Näihin vaihtoehtoihin sisältyy koneellinen juottaminen LGA tai BGA tavalla, RF-liittimien käyttö ja antenniryhmää varten kehitetty 16 porttinen liitin. Kyseisistä liitäntä vaihtoehdoista parhaaksi ja soveltuvimmaksi osoittautui LGA juotos. Tutkimustyö sisältää antennilevyn ja äitilevyn osittaisen suunnittelun ja optimoinnin, ja sen perusteella tehdyn prototyypin, mittaustulokset ja päätelmät liitynnän toimivuudesta. Prototyyppejä tehtiin kaikkiaan kuusi, joista viimeiset 3–6 olivat onnistuneita juotospaksuuden perusteella. Mittausten perusteella sovituksessa on paljon vaihtelua, jolle löydettiin muutamia syitä röntgen tarkastuksessa ja virheanalyysissa. Näihin syihin sisältyy juotoksesta löytyneet kaasukuplat, jotka johtavat juotoksen laajenemiseen horisontaalisesti, mikä taas heikentää maadoitusta ja täten sovitusta. Juotoksen kaasukuplat voidaan kuitenkin välttää niin kutsutulla juotoksen pallottamisella (Engl. Solder Bumping), jossa kaasukuplia ilmeni huomattavasti vähemmän ja ne olivat pienempiä. Lopputulemana todettiin, että työ on onnistunnut ja prototyyppi on toimiva, mutta tarjotut kehitysideat kannattaa huomioida mahdollisessa jatkokehityksessä ja simuloinnit tulisi tehdä uudelleen virheanalyysistä saaduilla arvoilla ja tiedoilla

Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

Développement d’un procédé d’électrodéposition séquentielle pour fabrication des microbilles à haute densité

Aujourd’hui l’industrie des semiconducteurs aborde une époque requérant le couplage de l’innovation au niveau de l'assemblage avec la mise à l’échelle des dispositifs. Cette dernière n’est plus l’élément clé qui propulse l’évolution technologique à cause de l’énorme investissement requis vis-à-vis sa rentabilité qui devient de plus en plus limitée. Avec la réorientation de l’intérêt de la majorité des acteurs vers l’innovation au niveau des assemblages, cette thèse s’inscrit dans un contexte d’amélioration de la fiabilité des assemblages de larges puces renversées pour le calul haute performance à travers le développement des microbilles de brasures à faible coût et de métallurgie optimisée. Des microbilles de brasure à faible coût et hétérogènes sont proposées comme une approche simple qui présente des bénéfices métallurgiques et économiques. D’une part, l’électrodéposition séquentielle des couches de Sn et Ag pures au lieu d’alliage est réalisée à un faible coût d’acquisition et avec une simplicité de maintenance. D’une autre part, la même installation d’électrodéposition de Sn et Ag purs peut servir à la fabrication d’une multitude de brasures avec différentes teneurs en Ag. Malgré le besoin d’une standardisation des procédés de fabrication des microbilles, les motivations citées précédemment peuvent constituer un facteur d’attraction pour l’industrie afin de l’adopter comme alternative à l’électrodéposition conventionnelle des alliages. En plus de son faible coût, l’approche de fabrication des microbilles par électrodéposition séquentielle amène une flexibilité métallurgique avec l’utilisation d’une barrière qui limite la diffusion d’Ag. Cette dernière résulte en une microbille de brasure unique, qui peut à la fois i) avoir une structure hétérogène avec une faible teneur en Ag dont la ductilité élevée est maintenue à proximité des couches fragiles de la métallisation de la puce lors des étapes de l’assemblage; ii) avoir une forme en pilier dont des bénéfices sont similaires à ceux du pilier en Cu en évitant les effets néfastes de sa rigidité sur les couches du BEOL. Les différentes étapes de fabrication des microbilles de brasure ont été développées en se limitant à des procédés qui peuvent être intégrés facilement dans un environnement de production industrielle. La manipulation de la métallurgie des joints de brasure a été réalisée avec succès en démontrant une structure hétérogène unique de brasure dans un assemblage de puces renversées

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Multiscale microstructures and microstructural effects on the reliability of microbumps in three-dimensional integration

The dimensions of microbumps in three-dimensional integration reach microscopic scales and thus necessitate a study of the multiscale microstructures in microbumps. Here, we present simulated mesoscale and atomic-scale microstructures of microbumps using phase field and phase field crystal models. Coupled microstructure, mechanical stress, and electromigration modeling was performed to highlight the microstructural effects on the reliability of microbumps. The results suggest that the size and geometry of microbumps can influence both the mesoscale and atomic-scale microstructural formation during solidification. An external stress imposed on the microbump can cause ordered phase growth along the boundaries of the microbump. Mesoscale microstructures formed in the microbumps from solidification, solid state phase separation, and coarsening processes suggest that the microstructures in smaller microbumps are more heterogeneous. Due to the differences in microstructures, the von Mises stress distributions in microbumps of different sizes and geometries vary. In addition, a combined effect resulting from the connectivity of the phase morphology and the amount of interface present in the mesoscale microstructure can influence the electromigration reliability of microbumps

Multiscale microstructures and microstructural effects on the reliability of microbumps in three-dimensional integration

The dimensions of microbumps in three-dimensional integration reach microscopic scales and thus necessitate a study of the multiscale microstructures in microbumps. Here, we present simulated mesoscale and atomic-scale microstructures of microbumps using phase field and phase field crystal models. Coupled microstructure, mechanical stress, and electromigration modeling was performed to highlight the microstructural effects on the reliability of microbumps. The results suggest that the size and geometry of microbumps can influence both the mesoscale and atomic-scale microstructural formation during solidification. An external stress imposed on the microbump can cause ordered phase growth along the boundaries of the microbump. Mesoscale microstructures formed in the microbumps from solidification, solid state phase separation, and coarsening processes suggest that the microstructures in smaller microbumps are more heterogeneous. Due to the differences in microstructures, the von Mises stress distributions in microbumps of different sizes and geometries vary. In addition, a combined effect resulting from the connectivity of the phase morphology and the amount of interface present in the mesoscale microstructure can influence the electromigration reliability of microbumps

Microstructural and mechanical characteristics of micro-scale intermetallic compounds interconnections

Following the continually increasing demand for high-density interconnection and multilayer packaging for chips, solder bump size has decreased significantly over the years, this has led to some challenges in the reliability of interconnects. This thesis presents research into the resulting effects of miniaturization on the interconnection with Sn-solder, especially focusing on the full intermetallics (IMCs) micro-joints which appear in the 3D IC stacking packaging. Thereby, systematic studies have been conducted to study the microstructural evolution and reliability issues of Cu-Sn and Cu-Sn-Ni IMCs micro-joints. (1) Phenomenon of IMCs planar growth: The planar IMCs interlayer was asymmetric and composed of (Cu,Ni)6Sn5 mainly in Ni/Sn (2.5~5 µm)/Cu interconnect. Meanwhile, it was symmetric two-layer structure in Cu/Sn (2.5~5 µm)/Cu interconnect with the Cu3Sn fine grains underneath Cu6Sn5 cobblestone-shape-like grains for each IMCs layer. Besides, it is worth noticing that the appearance of Cu-rich whiskers (the mixture of Cu/Cu2O/SnOx/Cu6Sn5) could potentially lead to short-circuit in the cases of ultra-fine (<10 µm pitch) interconnects for the miniaturization of electronics devices. (2) Microstructural evolution process of Cu-Sn IMCs micro-joint: The simultaneous solidification of IMCs interlayer supressed the scalloped growth of Cu6Sn5 grains in Cu/Sn (2.5 µm)/Cu interconnect during the transient liquid phase (TLP) soldering process. The growth factor of Cu3Sn was in the range of 0.29~0.48 in Cu-Cu6Sn5 diffusion couple at 240~290 °C, which was impacted significantly by the type of substrates. And the subsequent homogenization process of Cu3Sn grains was found to be consistent with the description of flux-driven ripening (FDR) theory. Moreover, Kirkendall voids appeared only in the Cu3Sn layer adjacent to Cu-plated substrate, and this porous Cu3Sn micro-joint was mechanically robust during the shear test. (3) Microstructural evolution of Cu-Sn-Ni IMCs micro-joint: There was obvious inter-reaction between the interfacial reactions in Ni/Sn (1.5 µm)/Cu interconnect. The growth factor of (Cu,Ni)3Sn on Cu side was about 0.36 at 240 °C, and the reaction product on Ni side was changed from Ni3Sn4 into (Cu,Ni)6Sn5 with the increase of soldering temperature. In particular, the segregation of Ni atoms occurred along with phase transformation at 290 °C and thereby stabilized the (Cu,Ni)6Sn5 phase for the high Ni content of 20 at.%. (4) Micro-mechanical characteristics of Cu-Sn-Ni IMCs micro-joint: The Young s modulus and hardness of Cu-Sn-Ni IMCs were measured by nanoindentation test, such as 160.6±3.1 GPa/ 7.34±0.14 GPa for (Cu,Ni)6Sn5 and 183.7±4.0 GPa/ 7.38±0.46 GPa for (Cu,Ni)3Sn, respectively. Besides, in-situ nano-compression tests have been conducted on IMCs micro-cantilevers, the fracture strength turns out to be 2.46 GPa. And also, the ultimate tensile stress was calculated to be 2.3±0.7 GPa from in-situ micro-bending tests, which is not sensitive with the microstructural change of IMCs after dwelling at 290 °C