A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units

This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synchronization error due to the local oscillator triggering the on-board timer. The SC has been implemented into a PMU prototype developed within the OpenPMU project using a BeagleBone Black (BBB) board. The distinctive feature of the proposed solution is its ability to track an input Pulse-Per-Second (PPS) reference with good long-term stability and with no need for specific on-board synchronization circuitry. Indeed, the SC implementation relies only on one co-processor for real-time application and requires just an input PPS signal that could be distributed from a single substation clock

Cross-Layer Adaptive Feedback Scheduling of Wireless Control Systems

There is a trend towards using wireless technologies in networked control systems. However, the adverse properties of the radio channels make it difficult to design and implement control systems in wireless environments. To attack the uncertainty in available communication resources in wireless control systems closed over WLAN, a cross-layer adaptive feedback scheduling (CLAFS) scheme is developed, which takes advantage of the co-design of control and wireless communications. By exploiting cross-layer design, CLAFS adjusts the sampling periods of control systems at the application layer based on information about deadline miss ratio and transmission rate from the physical layer. Within the framework of feedback scheduling, the control performance is maximized through controlling the deadline miss ratio. Key design parameters of the feedback scheduler are adapted to dynamic changes in the channel condition. An event-driven invocation mechanism for the feedback scheduler is also developed. Simulation results show that the proposed approach is efficient in dealing with channel capacity variations and noise interference, thus providing an enabling technology for control over WLAN.Comment: 17 pages, 12 figures; Open Access at http://www.mdpi.org/sensors/papers/s8074265.pd

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

FPGA-based Low-Latency Audio Coprocessor for Networked Music Performance

Networked Music Performance (NMP) applications are acknowledged to be a particularly challenging field due to their stringent latency requirements and their demand for high audio quality. Most solutions developed in the last decades tried to overcome these obstacles by leveraging software approaches, that can introduce excessive time delays as a consequence of the general-purpose nature of the architectures on which they are implemented. Alternatively, a dedicated audio processor can be employed to minimize the mouth-to-ear latency.This paper presents the ongoing development of an hardware system that exploits an Application-Specific Instruction set Processor (ASIP) implemented on a Field-Programmable Gate Array (FPGA) to accelerate audio sample management. Specifically, a Transport Triggered Architecture (TTA) is being investigated as a processor design that aligns well with the required application domains. Preliminary empirical results indicate that the proposed solution has the potential to achieve extremely low latency, compatible with NMP requirements. Further optimizations and enhancements are actively being pursued to address the yet open challenges posed by NMP applications

Traffic Signal Consensus Control

We introduce a model for traffic signal management based on network consensus control principles. The underlying principle in a consensus approach is that traffic signal cycles are adjusted in a distributed way so as to achieve desirable ratios of queue lengths throughout the street network. This approach tends to reduce traffic congestion due to queue saturation at any particular city block and it appears less susceptible to congestion due to unexpected traffic loads on the street grid. We developed simulation tools based on the MATLAB computing environment to analyze the use of the mathematical consensus approach to manage the signal control on an urban street network

STABILITY AND PERFORMANCE OF NETWORKED CONTROL SYSTEMS

Network control systems (NCSs), as one of the most active research areas, are arousing comprehensive concerns along with the rapid development of network. This dissertation mainly discusses the stability and performance of NCSs into the following two parts. In the first part, a new approach is proposed to reduce the data transmitted in networked control systems (NCSs) via model reduction method. Up to our best knowledge, we are the first to propose this new approach in the scientific and engineering society. The "unimportant" information of system states vector is truncated by balanced truncation method (BTM) before sending to the networked controller via network based on the balance property of the remote controlled plant controllability and observability. Then, the exponential stability condition of the truncated NCSs is derived via linear matrix inequality (LMI) forms. This method of data truncation can usually reduce the time delay and further improve the performance of the NCSs. In addition, all the above results are extended to the switched NCSs. The second part presents a new robust sliding mode control (SMC) method for general uncertain time-varying delay stochastic systems with structural uncertainties and the Brownian noise (Wiener process). The key features of the proposed method are to apply singular value decomposition (SVD) to all structural uncertainties, to introduce adjustable parameters for control design along with the SMC method, and new Lyapunov-type functional. Then, a less-conservative condition for robust stability and a new robust controller for the general uncertain stochastic systems are derived via linear matrix inequality (LMI) forms. The system states are able to reach the SMC switching surface as guaranteed in probability 1 by the proposed control rule. Furthermore, the novel Lyapunov-type functional for the uncertain stochastic systems is used to design a new robust control for the general case where the derivative of time-varying delay can be any bounded value (e.g., greater than one). It is theoretically proved that the conservatism of the proposed method is less than the previous methods. All theoretical proofs are presented in the dissertation. The simulations validate the correctness of the theoretical results and have better performance than the existing results

Clock Synchronization between Observational Units in the Arctic Tundra

The arctic tundra is one of the ecosystems that is most affected by climate changes. The effects of these changes on the wildlife in the arctic are therefore critical to monitor. To monitor the changes, small computing devices with sensors and cameras, known as Observational Units, can be used. Using a cluster network of interconnected observational units, so that data can be reported from the most distant nodes to a homebase, introduces problems as the node’s local clocks tend to skew away from each other based on the environment they are in. This thesis aims to address the problem of clock synchronization in cluster networks that are disconnected from constant power and the internet. This thesis describes how we designed, built, and tested a prototype software solution for an interconnected Wireless Sensor Network using observational units built for arctic climates. We designed and built a two-phased system where the nodes dynamically join a network and synchronize their duty cycling and clocks with each other, creating a synchronized cluster of nodes that allows for data to be propagated, where any of the nodes can become sink nodes if they have a connection to a homebase. The nodes use a built-in clock synchronization operation to achieve synchronized clocks across the cluster network. The prototype system can perform the operations as planned. However, the results show that the system scales poorly when introducing new sinks to the network while running in the operational phase, as the paths shared scales exponentially, in contrast to when a sink is introduced in the starting phase of the system, where the transmissions grow linearly with a degree based on the number of nodes in the network. The time synchronization experiments also showed that the network is able to remain synchronized, although transmission number is a concern when the network does not have any sink nodes