Design synthesis for dynamically reconfigurable logic systems

Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced reconfigurable logic design expert. This thesis proposes an automatic synthesis method which relieves designers of some of the difficulties associated with designing partially dynamically reconfigurable systems. A new design abstraction model for reconfigurable systems is proposed in order to support design exploration using the presented method. Given an input behavioural model, a technology server and a set of design constraints, the method will generate a reconfigurable design solution in the form of a 3D floorplan and a configuration schedule. The approach makes use of genetic algorithms. It facilitates global optimisation to accommodate multiple design objectives common in reconfigurable system design, while making realistic estimates of configuration overheads and of the potential for resource sharing between configurations. A set of custom evolutionary operators has been developed to cope with a multiple-objective search space. Furthermore, the application of a simulation technique verifying the lll results of such an automatic exploration is outlined in the thesis. The qualities of the proposed method are evaluated using a set of benchmark designs taking data from a real reconfigurable logic technology. Finally, some extensions to the proposed method and possible research directions are discussed

フロアプラン指向高位合成手法とイジング計算機応用に関する研究

早大学位記番号:新7790早稲田大

Voltage island based heterogeneous NoC design through constraint programming

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature. © 2014 Elsevier Ltd. All rights reserved

Characterization and Avoidance of Critical Pipeline Structures in Aggressive Superscalar Processors

In recent years, with only small fractions of modern processors now accessible in a single cycle, computer architects constantly fight against propagation issues across the die. Unfortunately this trend continues to shift inward, and now the even most internal features of the pipeline are designed around communication, not computation. To address the inward creep of this constraint, this work focuses on the characterization of communication within the pipeline itself, architectural techniques to avoid it when possible, and layout co-design for early detection of problems. I present work in creating a novel detection tool for common case operand movement which can rapidly characterize an applications dataflow patterns. The results produced are suitable for exploitation as a small number of patterns can describe a significant portion of modern applications. Work on dynamic dependence collapsing takes the observations from the pattern results and shows how certain groups of operations can be dynamically grouped, avoiding unnecessary communication between individual instructions. This technique also amplifies the efficiency of pipeline data structures such as the reorder buffer, increasing both IPC and frequency. I also identify the same sets of collapsible instructions at compile time, producing the same benefits with minimal hardware complexity. This technique is also done in a backward compatible manner as the groups are exposed by simple reordering of the binarys instructions. I present aggressive pipelining approaches for these resources which avoids the critical timing often presumed necessary in aggressive superscalar processors. As these structures are designed for the worst case, pipelining them can produce greater frequency benefit than IPC loss. I also use the observation that the dynamic issue order for instructions in aggressive superscalar processors is predictable. Thus, a hardware mechanism is introduced for caching the wakeup order for groups of instructions efficiently. These wakeup vectors are then used to speculatively schedule instructions, avoiding the dynamic scheduling when it is not necessary. Finally, I present a novel approach to fast and high-quality chip layout. By allowing architects to quickly evaluate what if scenarios during early high-level design, chip designs are less likely to encounter implementation problems later in the process.Ph.D.Committee Chair: Scott Wills; Committee Member: David Schimmel; Committee Member: Gabriel Loh; Committee Member: Hsien-Hsin Lee; Committee Member: Yorai Ward

B*tree representation based thermal and variability aware floorplanning frame work

Master'sMASTER OF ENGINEERIN

High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms

There is a growing interest in deploying commercial SRAM-based Field Programmable Gate Array (FPGA) circuits in space due to their low cost, reconfigurability, high logic capacity and rich I/O interfaces. However, their configuration memory (CM) is vulnerable to ionising radiation which raises the need for effective fault-tolerant design techniques. This thesis provides the following contributions to mitigate the negative effects of soft errors in SRAM FPGA circuits. Triple Modular Redundancy (TMR) with periodic CM scrubbing or Module-based CM error recovery (MER) are popular techniques for mitigating soft errors in FPGA circuits. However, this thesis shows that MER does not recover CM soft errors in logic instantiated outside the reconfigurable regions of TMR modules. To address this limitation, a hybrid error recovery mechanism, namely FMER, is proposed. FMER uses selective periodic scrubbing and MER to recover CM soft errors inside and outside the reconfigurable regions of TMR modules, respectively. Experimental results indicate that TMR circuits with FMER achieve higher dependability with less energy consumption than those using periodic scrubbing or MER alone. An imperative component of MER and FMER is the reconfiguration control network (RCN) that transfers the minority reports of TMR components, i.e., which, if any, TMR module needs recovery, to the FPGA's reconfiguration controller (RC). Although several reliable RCs have been proposed, a study of reliable RCNs has not been previously reported. This thesis fills this research gap, by proposing a technique that transfers the circuit's minority reports to the RC via the configuration-layer of the FPGA. This reduces the resource utilisation of the RCN and therefore its failure rate. Results show that the proposed RCN achieves higher reliability than alternative RCN architectures reported in the literature. The last contribution of this thesis is a high-level synthesis (HLS) tool, namely TLegUp, developed within the LegUp HLS framework. TLegUp triplicates Xilinx 7-series FPGA circuits during HLS rather than during the register-transfer level pre- or post-synthesis flow stage, as existing computer-aided design tools do. Results show that TLegUp can generate non-partitioned TMR circuits with 500x less soft error sensitivity than non-triplicated functional equivalent baseline circuits, while utilising 3-4x more resources and having 11% lower frequency

Placement and routing for cross-referencing digital microfluidic biochips.

Xiao, Zigang."October 2010."Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.Includes bibliographical references (leaves 62-66).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.viChapter 1 --- Introduction --- p.1Chapter 1.1 --- Microfluidic Technology --- p.2Chapter 1.1.1 --- Continuous Flow Microfluidic System --- p.2Chapter 1.1.2 --- Digital Microfluidic System --- p.2Chapter 1.2 --- Pin-Constrained Biochips --- p.4Chapter 1.2.1 --- Droplet-Trace-Based Array Partitioning Method --- p.5Chapter 1.2.2 --- Broadcast-addressing Method --- p.5Chapter 1.2.3 --- Cross-Referencing Method --- p.6Chapter 1.2.3.1 --- Electrode Interference in Cross-Referencing Biochips --- p.7Chapter 1.3 --- Computer-Aided Design Techniques for Biochip --- p.8Chapter 1.4 --- Placement Problem in Biochips --- p.8Chapter 1.5 --- Droplet Routing Problem in Cross-Referencing Biochips --- p.11Chapter 1.6 --- Our Contributions --- p.14Chapter 1.7 --- Thesis Organization --- p.15Chapter 2 --- Literature Review --- p.16Chapter 2.1 --- Introduction --- p.16Chapter 2.2 --- Previous Works on Placement --- p.17Chapter 2.2.1 --- Basic Simulated Annealing --- p.17Chapter 2.2.2 --- Unified Synthesis Approach --- p.18Chapter 2.2.3 --- Droplet-Routing-Aware Unified Synthesis Approach --- p.19Chapter 2.2.4 --- Simulated Annealing Using T-tree Representation --- p.20Chapter 2.3 --- Previous Works on Routing --- p.21Chapter 2.3.1 --- Direct-Addressing Droplet Routing --- p.22Chapter 2.3.1.1 --- A* Search Method --- p.22Chapter 2.3.1.2 --- Open Shortest Path First Method --- p.23Chapter 2.3.1.3 --- A Two Phase Algorithm --- p.24Chapter 2.3.1.4 --- Network-Flow Based Method --- p.25Chapter 2.3.1.5 --- Bypassibility and Concession Method --- p.26Chapter 2.3.2 --- Cross-Referencing Droplet Routing --- p.28Chapter 2.3.2.1 --- Graph Coloring Method --- p.28Chapter 2.3.2.2 --- Clique Partitioning Method --- p.30Chapter 2.3.2.3 --- Progressive-ILP Method --- p.31Chapter 2.4 --- Conclusion --- p.32Chapter 3 --- CrossRouter for Cross-Referencing Biochip --- p.33Chapter 3.1 --- Introduction --- p.33Chapter 3.2 --- Problem Formulation --- p.34Chapter 3.3 --- Overview of Our Method --- p.35Chapter 3.4 --- Net Order Computation --- p.35Chapter 3.5 --- Propagation Stage --- p.36Chapter 3.5.1 --- Fluidic Constraint Check --- p.38Chapter 3.5.2 --- Electrode Constraint Check --- p.38Chapter 3.5.3 --- Handling 3-pin net --- p.44Chapter 3.5.4 --- Waste Reservoir --- p.45Chapter 3.6 --- Backtracking Stage --- p.45Chapter 3.7 --- Rip-up and Re-route Nets --- p.45Chapter 3.8 --- Experimental Results --- p.46Chapter 3.9 --- Conclusion --- p.47Chapter 4 --- Placement in Cross-Referencing Biochip --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- Problem Formulation --- p.50Chapter 4.3 --- Overview of the method --- p.50Chapter 4.4 --- Dispenser and Reservoir Location Generation --- p.51Chapter 4.5 --- Solving Placement Problem Using ILP --- p.51Chapter 4.5.1 --- Constraints --- p.53Chapter 4.5.1.1 --- Validity of modules --- p.53Chapter 4.5.1.2 --- Non-overlapping and separation of Modules --- p.53Chapter 4.5.1.3 --- Droplet-Routing length constraint --- p.54Chapter 4.5.1.4 --- Optical detector resource constraint --- p.55Chapter 4.5.2 --- Objective --- p.55Chapter 4.5.3 --- Problem Partition --- p.56Chapter 4.6 --- Pin Assignment --- p.56Chapter 4.7 --- Experimental Results --- p.57Chapter 4.8 --- Conclusion --- p.59Chapter 5 --- Conclusion --- p.60Bibliography --- p.6

Simulated Annealing

The book contains 15 chapters presenting recent contributions of top researchers working with Simulated Annealing (SA). Although it represents a small sample of the research activity on SA, the book will certainly serve as a valuable tool for researchers interested in getting involved in this multidisciplinary field. In fact, one of the salient features is that the book is highly multidisciplinary in terms of application areas since it assembles experts from the fields of Biology, Telecommunications, Geology, Electronics and Medicine