An enhancing fault current limitation hybrid droop/V-f control for grid-tied four-wire inverters in AC microgrids

Microgrid integration and fault protection in complex network scenarios is a coming challenge to be faced with new strategies and solutions. In this context of increasing complexity, this paper describes two specific overload control strategies for four-wire inverters integrated in low voltage four-wire alternating current (AC) microgrids. The control of grid-tied microgrid inverters has been widely studied in the past and mainly focused on the use of droop control, which hugely constrains the time response during grid-disconnected operation. Taking into account the previous knowledge and experience about this subject, the main contribution of these two proposals regards providing fault current limitation in both operation modes, over-load capability skills in grid-connected operation and sinusoidal short-circuit proof in grid-disconnected operation. In the complex operation scenarios mentioned above, a hybrid combination of AC droop control based on dynamic phasors with varying virtual resistance, and voltage/frequency master voltage control for grid-(dis)connected operation modes are adopted as the mechanism to enhance time response. The two proposals described in the present document are validated by means of simulations using Matlab/Simulink and real experimental results obtained from CENER (The National Renewable Energy Centre) experimental ATENEA four-wire AC microgrid, obtaining time responses in the order of two-three grid cycles for all cases.Postprint (published version

High-power converters for space applications

Phase 1 was a concept definition effort to extend space-type dc/dc converter technology to the megawatt level with a weight of less than 0.1 kg/kW (220 lb./MW). Two system designs were evaluated in Phase 1. Each design operates from a 5 kV stacked fuel cell source and provides a voltage step-up to 100 kV at 10 A for charging capacitors (100 pps at a duty cycle of 17 min on, 17 min off). Both designs use an MCT-based, full-bridge inverter, gaseous hydrogen cooling, and crowbar fault protection. The GE-CRD system uses an advanced high-voltage transformer/rectifier filter is series with a resonant tank circuit, driven by an inverter operating at 20 to 50 kHz. Output voltage is controlled through frequency and phase shift control. Fast transient response and stability is ensured via optimal control. Super-resonant operation employing MCTs provides the advantages of lossless snubbing, no turn-on switching loss, use of medium-speed diodes, and intrinsic current limiting under load-fault conditions. Estimated weight of the GE-CRD system is 88 kg (1.5 cu ft.). Efficiency of 94.4 percent and total system loss is 55.711 kW operating at 1 MW load power. The Maxwell system is based on a resonance transformer approach using a cascade of five LC resonant sections at 100 kHz. The 5 kV bus is converted to a square wave, stepped-up to a 100 kV sine wave by the LC sections, rectified, and filtered. Output voltage is controlled with a special series regulator circuit. Estimated weight of the Maxwell system is 83.8 kg (4.0 cu ft.). Efficiency is 87.2 percent and total system loss is 146.411 kW operating at 1 MW load power

Health Condition Monitoring and Fault-Tolerant Operation of Adjustable Speed Drives

Adjustable speed drives (ASDs) have been extensively used in industrial applications over the past few decades because of their benefits of energy saving and control flexibilities. However, the wider penetration of ASD systems into industrial applications is hindered by the lack of health monitoring and fault-tolerant operation techniques, especially in safety-critical applications. In this dissertation, a comprehensive portfolio of health condition monitoring and fault-tolerant operation strategies is developed and implemented for multilevel neutral-point-clamped (NPC) power converters in ASDs. Simulations and experiments show that these techniques can improve power cycling lifetime of power transistors, on-line diagnosis of switch faults, and fault-tolerant capabilities.The first contribution of this dissertation is the development of a lifetime improvement Pulse Width Modulation (PWM) method which can significantly extend the power cycling lifetime of Insulated Gate Bipolar Transistors (IGBTs) in NPC inverters operating at low frequencies. This PWM method is achieved by injecting a zero-sequence signal with a frequency higher than that of the IGBT junction-to-case thermal time constants. This, in turn, lowers IGBT junction temperatures at low output frequencies. Thermal models, simulation and experimental verifications are carried out to confirm the effectiveness of this PWM method. As a second contribution of this dissertation, a novel on-line diagnostic method is developed for electronic switch faults in power converters. Targeted at three-level NPC converters, this diagnostic method can diagnose any IGBT faults by utilizing the information on the dc-bus neutral-point current and switching states. This diagnostic method only requires one additional current sensor for sensing the neutral-point current. Simulation and experimental results verified the efficacy of this diagnostic method.The third contribution consists of the development and implementation of a fault-tolerant topology for T-Type NPC power converters. In this fault-tolerant topology, one additional phase leg is added to the original T-Type NPC converter. In addition to providing a fault-tolerant solution to certain switch faults in the converter, this fault-tolerant topology can share the overload current with the original phase legs, thus increasing the overload capabilities of the power converters. A lab-scale 30-kVA ASD based on this proposed topology is implemented and the experimental results verified its benefits

Fault detection in a three-phase inverter fed circuit: Enhancing the Tripping capability of a UPS circuit breaker using wave shape recognition algorithm

Uninterruptible power supplies (UPS) are electrical devices that protect sensitive loads from power line disturbances such as source side overcurrents caused by overvoltage and power surges. The critical load in a double conversion UPS system is supplied from an invert-er. When overcurrents occur on the load side of double conversion UPS systems, both the UPS system’s inverter and the critical load connected to it stand a high risk of damage. Load side overcurrents due to short circuits, ground faults and motor/transformer start-up are very damaging to power electronic components, electrical equipment and cable connections. There exists circuit breakers on the load side designed to trip when a huge overcurrent occurs, thereby clearing the fault. A circuit breaker is normally sized and installed based on the maxi-mum capacity of the host system and trips when a predetermined overcurrent is recorded within a specific period of time. The UPS system’s inverter has a pre-set current limit value to protect insulated-gate bipolar transistors (IGBTs) from damage. During an overcurrent, invert-ers can supply a fault current whose peak value is limited to the IGBT current limit value. This inverter supplied fault current is not high enough to trip the circuit breaker. After an extended period of overcurrent, UPS internal tripping will be activated and all loads lose power. Opera-tion of the UPS in bypass mode supplies the required fault current but exposes the sensitive load to power line distortions. Therefore, it is desired to always supply the critical load via the inverter. This study targets to design a detection algorithm for short circuits and ground faults with a detection time faster than the UPS system’s internal tripping in order to isolate the faulted ar-ea, when the inverter is supplying the critical load. To achieve this, first, a MATLAB model was designed to aid in preliminary studies of fault detection through analysing the system behaviour. Secondly, literature review was conducted and a fault detection method selected with the help of the MATLAB model. Next, laboratory tests on a real UPS system were carried out and compared to the MATLAB results. Lastly, the detection algorithm was designed, im-plemented and tested on a real double conversion UPS system. The test results indicate that the implemented detection algorithm successfully detects short circuits and ground faults well within the desired time. It also successfully distinguishes short circuits and ground faults from other sources of overcurrents such as overloading and transformer inrush current. Future development of this study includes additional features such as a fault classification method proposed for implementation to improve the UPS debugging process during maintenance. Moreover, the detection algorithm will also be refined and devel-oped further to activate a circuit that discharges a current pulse to increase the fault current fed to the circuit breaker

Unified Power Quality Conditioner: protection and performance enhancement

The proliferation of power electronics-based equipment has produced a significant impact on the quality of electric power supply. Nowadays, much of the equipment is based on power electronic devices, often leading to problems of power quality. At the same time this equipment is typically equipped with microprocessor-based controllers which are quite sensitive to deviations from the ideal sinusoidal line voltage. Conventional power quality mitigation equipment is proving to be inadequate for an increasing number of applications, and this fact has attracted the attention of power engineers to develop dynamic and adjustable solutions to power quality problems. One modern and very promising solution that deals with both load current and supply voltage imperfections is the Unified Power Quality Conditioner (UPQC). This thesis investigates the development of UPQC protection scheme and control algorithms for enhanced performance. This work is carried out on a 12 kVA prototype UPQC. In order to protect the series inverter of the UPQC from overvoltage and overcurrent during short circuits on the load side of the UPQC, the secondary of the series transformer has to be short-circuited in a reasonably short time (microseconds). A hardware-based UPQC protection scheme against the load side short circuits is derived and its implementation and effectiveness is investigated. The main protection element is a crowbar connected across the secondary of the series transformer and consisting of a pair of antiparallel connected thyristors, which is governed by a very simple Zener diode based control circuit. Also, the software-based UPQC protection approach is investigated, the implementation of which does not require additional hardware

Control of Four-Wire Inverter-Interfaced DGs for Accurate Fault Type Classification

Inverter-interfaced distributed generators (IIDGs) generate fault currents that are different from those generated by conventional synchronous generators (SGs). As a result, commercial relays—that utilize current-angle-based phase selection measurements—misidentify faulty phase(s), which adversely impact the grid resiliency and reliability. In this thesis, a new control scheme is proposed to regulate the sequence components of the IIDG currents during unbalanced faults to ensure accurate fault type classification by commercial relays. The proposed controller controls the positive-sequence and negative-sequence currents in the dq-frame with a decoupled synchronous reference frame (DDSRF) based phase-locked loop (PLL) for components extraction and synchronization. It also uses a second order generalized integrator (SOGI) based PLL to synchronize the zero-sequence components. This scheme forces the angles of the negative-sequence and zero-sequence fault IIDG currents to behave like those of an SG while preserving the inverter’s current limits. This leads to proper fault type classification. The proposed control scheme pertains to three-wire IIDGs as well as four-wire IIDGs, which are common in low-voltage distribution networks. A performance evaluation using time-domain simulations is used on a benchmark network to confirm the success of the proposed control scheme under different fault conditions