Built-in self test of high speed analog-to-digital converters

Signals found in nature need to be converted to the digital domain through analog-to-digital converters (ADCs) to be processed by digital means [1]. For applications in communication and measurement [2], [3], high conversion rates are required. With advances of the complementary metal oxide semiconductor (CMOS) technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT) and to collect and analyze their responses.publishe

A Robust High Precision Algorithm for Sinewave Parameter Estimation

The estimation of sinewave parameters has many practical applications in test and data processing systems. Measuring the effective bits of an analog-to-digital converter and linear circuit identification are some typical examples. If a sinew ave\u27s frequency is known, there is an established linear method to estimate the other parameters. But when none of the parameters are known (which is usually the case in practical situations), the estimation problem becomes more difficult. Traditional approaches to this task applied an iterative, sinewave curve-fit algorithm. Two problems with this technique are that convergence is often slow and not always guaranteed and the results of different trials may be inconsistent due to trapping at a local minimum. Recently, a non-iterative algorithm has been developed which computes all four sine wave parameters directly. The algorithm combines a nonlinear technique and windowing to compute the estimates. Although this method is faster and more consistent than the curve-fit approach, one disadvantage is that the accuracy of some estimates tends to deteriorate rapidly if the sinusoid is corrupted by a high level of noise distortion. This study presents an improved algorithm to extract the four parameters of an unknown sinusoid from a sampled data record even though the samples may be distorted by a high level of noise. Given this record, the proposed method first computes the FFT (Fast Fourier Transform) of the data. Analysis of the resulting frequency spectrum provides a rough estimate of the sinewave\u27s fundamental frequency. Next, a bandpass filter designed around this frequency is used to eliminate much of the noise from the samples. Applying the existing four-parameter estimation algorithm to the filtered data, yields a more accurate frequency estimate. Finally, this new value, together with the original (noisy) data record is input to the three-parameter estimation algorithm to determine the remaining sinewave parameters. Simulation results indicate this proposed (new) algorithm not only shows substantial improvement in the accuracy of parameter estimates, but also produces consistent results for higher levels of noise distortion than previous methods have achieved

Frequency-domain characterization of random demodulation analog-to-information converters

The paper aims at proposing test methods for Analog-to-Information Converters (AICs).In particular, the objective of this work is to verify if figures of merit and test methods, currently defined in standards for traditional Analog-to-Digital Converters, can be applied to AICs based on the random demodulation architecture.For this purpose, an AIC prototype has been designed, starting from commercially available integrated circuits. A simulation analysis and an experimental investigation have been carried out to study the additional influencing factors such as the parameters of the reconstruction algorithm. Results show that standard figures of merit are in general capable of describing the performance of AICs, provided that they are slightly modified according to the proposals reported in the paper. In addition, test methods have to be modified in order to take into account the statistical behavior of AICs.</p

A re-configurable pipeline ADC architecture with built-in self-test techniques

High-performance analog and mixed-signal integrated circuits are integral parts of today\u27s and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they\u27re operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs.;In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved.;A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications.;To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC\u27s 0.25mum single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-gain bandwidth. The experimental results strongly support the effectiveness of reconfiguration algorithm, which provides an average of 0.5bit ENOB improvement among the set of configurations. For many applications, this is a very significant performance improvement.;The BIST and re-configurability techniques proposed are not limited to pipeline ADCs only. The BIST methodology is applicable to many analog systems and the re-configurability is applicable to any analog pipeline system

A Pipeline Analog-To-Digital Converter for a Plasma Impedance Probe

Space instrumentation technology is an essential tool for rocket and satellite research, and is expected to become popular in commercial and military operations in fields such as radar, imaging, and communications. These instruments are traditionally implemented on printed circuit boards using discrete general-purpose Analog-to-Digital Converter (ADC) devices and other components. A large circuit board is not convenient for use in micro-satellite deployments, where the total payload volume is limited to roughly one cubic foot. Because micro-satellites represent a fast growing trend in satellite research and development, there is motivation to explore miniaturized custom application-specific integrated circuit (ASIC) designs to reduce the volume and power consumption occupied by instrument electronics. In this thesis, a model of a new Plasma Impedance Probe (PIP) architecture, which utilizes a custom-built ADC along with other analog and digital components, is proposed. The model can be fully integrated to produce a low-power, miniaturized impedance probe

Error Compensation in Pipeline and Converters

This thesis provides an improved calibration and compensation scheme for pipeline Analog-to-Digital Converters (ADCs). This new scheme utilizes the intermediate stage outputs in a pipeline to characterize error mechanisms in the architecture. The goal of this compensation scheme is to increase the dynamic range of the ADC. The pipeline architecture is described in general, and tailored to the 1.5 bitslstage topology. Dominant error mechanisms are defined and characterized for an arbitrary stage in the pipeline. These error mechanisms are modeled with basis functions. The traditional calibration scheme is modified and used to iteratively calculate the error characteristics. The information from calibration is used to compensate the ADC. The calibration and compensation scheme is demonstrated both in simulation and using a custom hardware pipeline ADC. A 10-bit 5 MHz ADC was designed and fabricated in 0.5 pm CMOS to serve as the demonstration platform. The scheme was successful in showing improvements in dynamic range while using intermediate stage outputs to efficiently model errors in a pipeline stage. An application of the technique on the real converter showed an average of 8.6 dB improvement in SFDR in the full Nyquist band of the ADC. The average improvement in SINAD and ENOB are 3.2 dB and 0.53 bits respectively

Automatic Test Card – LINAC4 SPL

In order to fully characterize an analogue to digital converter its linearity, distortion, cross talk etc. must be measured. This can be done by supplying known test signals to each of its inputs and analysing the digital values read from the device

Accurate and robust spectral testing with relaxed instrumentation requirements

Spectral testing has been widely used to characterize the dynamic performances of the electrical signals and devices, such as Analog-to-Digital Converters (ADCs) for many decades. One of the difficulties faced is to accurately and cost-effectively test the continually higher performance devices. Standard test methods can be difficult to implement accurately and cost effectively, due to stringent requirements. To relax these necessary conditions and to reduce test costs, while achieving accurate spectral test results, several new algorithms are developed to perform accurate spectral and linearity test without requiring precise, expensive instruments. In this dissertation, three classes of methods for overcoming the above difficulties are presented. The first class of methods targeted the accurate, single-tone spectral testing. The first method targets the non-coherent sampling issue on spectral testing, especially when the non-coherently sampled signal has large distortions. The second method resolves simultaneous amplitude and frequency drift with non-coherent sampling. The third method achieves accurate linearity results for DAC-ADC co-testing, and generates high-purity sine wave using the nonlinear DAC in the system via pre-distortion. The fourth method targets ultra-pure sine wave generation with two nonlinear DACs, two simple filters, and a nonlinear ADC. These proposed methods are validated by both simulation and measurement results, and have demonstrated their high accuracy and robustness against various test conditions. The second class of methods deals with the accurate multi-tone spectral testing. The first method in this class resolves the non-coherent sampling issue in multi-tone spectral testing. The second method in this class introduces another proposed method to deal with multi-tone impure sources in spectral testing. The third method generates the multi-tone sine wave with minimum peak-to-average power ratio, which can be implemented in many applications, such as spectral testing and signal analysis. Similarly, simulation and measurement results validate the functionality and robustness of these proposed methods. Finally, the third class introduces two proposed methods to accurately test linearity characteristics of high-performance ADCs using low purity sinusoidal or ramp stimulus in the presence of flicker noise. Extensive simulation results have verified their effectiveness to reduce flicker noise influence and achieve accurate linearity results

ADC standard IEC 60748-4-3: precision measurement of alternative ENOB without a sine wave

A practical analog-to-digital converter (ADC) introduces quantization error in excess of the ideal value and one way of expressing this is by comparing the value of this error with that of an ideal ADC. This comparison is known as the effective number of bits (ENOBs). It is accepted practice to measure ENOB using the signal-to-noise and distortion (SINAD) ratio of a sine-wave input. This paper extends ENOB theory to any arbitrary waveform by including the crest factor of the input signal. It is now possible to apply the ENOB concept to wideband systems. Measuring the SINAD of an arbitrary or multitone waveform with precision normally requires the use of laboratory standard test equipment. However, International Electrotechnical Commission standard 60748-4-3 specifies an alternative method for wideband SINAD measurements that may also be suitable for built-in test. It is essentially a multitone test using two pseudorandom signal sources and is sometimes known as the double comb-filter (DCF) method. This paper demonstrates the requirements for a practical implementation of a DCF-based system for measuring an ENOB of up to 24 bits. It is shown that in a practical application, DCF ENOB and sine-wave ENOB results have similar levels of accuracy, but in the presence of amplitude nonlinearity the differing test signal amplitude weightings cannot fundamentally produce the same ENOB figure. It is shown that DCF ENOB is more representative of communications system performance and therefore extends the use of ENOB to wideband application

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009