Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Méthodes de mesure pour l’analyse vectorielle aux fréquences millimétriques en technologie intégrée

This thesis focuses on the study of vectorial measurement methods for analysing microelectronic circuits in integrated technology at millimeter wave frequencies. Current calibration and de-embedding methods are less precise for successfully extracting the intrinsic parameters of devices and circuits at millimeter wave frequencies, while the targeted operating frequencies are above 100 GHz. This is especially true for the characterization of passive devices such as propagation lines. The initial motivation of this thesis work was to explain the exact origin of the additional loss measured in Slow-Wave Coplanar Waveguides (S-CPW) lines at millimeter wave frequencies. Was it a problem of raw measurement or a problem of de-embedding method, which underestimates the losses? Or was it a problem of insufficient modeling of the effects of adjacent cells, or even the creation of a perturbation mode of propagation?This work consists of estimating many de-embedding methods beyond 65 GHz and classifies these methods into three groups to be able to compare them in a meaningful way. This study was conducted in three phases.In the first phase, we compared all the de-embedding methods with known electrical model parasitics of pad/accessline. This phase identifies the optimal conditions to use and apply these de-embedding methods.In the second phase, the modeling of test structures is performed using a 3D electromagnetic simulator based on finite element method. This phase tested the robustness of the methods and considered an original de-embedding method called Half-Thru de-embedding method. This method gives comparable results to the TRL method, which remains the most effective method. However, it remains difficult to explain the origin of additional losses obtained in measured S-CPW line.A third modeling phase was analysed to take into account the measurement of probes and the adjacent cells near our device under test. More than 80 test structures were designed in AMS 0.35 μm CMOS technology to compare the different de-embedding methods and analyse the link with adjacent cells, measuring probes and perturbation mode of propagation.Finally, this work has identified a number of precautions to consider for the attention of microelectronic circuit designers wishing to characterize their circuit with precision beyond 110 GHz. It also helped to establish Half-Thru Method de-embedding method, which is not based on electrical model, unlike other methods.Cette thèse porte sur l’étude des méthodes de mesure pour l’analyse vectorielle des circuits microélectroniques en technologie intégrée aux fréquences millimétriques. Pour réussir à extraire les paramètres intrinsèques de circuits réalisés aux longueurs d'ondes millimétriques, les méthodes actuelles de calibrage et de de-embedding sont d'autant moins précises que les fréquences de fonctionnement visées augmentent au-delà de 100 GHz notamment. Cela est d’autant plus vrai pour la caractérisation des dispositifs passifs tels que des lignes de propagation. La motivation initiale de ces travaux de thèse venait du fait qu'il était difficile d'expliquer l’origine exacte des pertes mesurées pour des lignes coplanaires à ondes lentes (lignes S-CPW) aux fréquences millimétriques. Etait-ce un problème de mesure brute, un problème de méthode de-embedding qui sous-estime les pertes, une modélisation insuffisante des effets des cellules adjacentes, ou encore la création d'un mode de propagation perturbatif ?Le travail a principalement consisté à évaluer une dizaine de méthodes de de-embedding au-delà de 65 GHz et à classifier ces méthodes en 3 groupes pour pouvoir les comparer de manière pertinente. Cette étude s’est déroulée en 3 phases.Dans la première phase, il s’agissait de comparer les méthodes de de-embedding tout en maitrisant les modèles électriques des plots et des lignes d’accès. Cette phase a permis de dégager les conditions optimales d’utilisation pour pouvoir appliquer ces différentes méthodes de de-embedding.Dans la deuxième phase, la modélisation des structures de test a été réalisée à l’aide d’un simulateur électromagnétique 3D basé sur la méthode des éléments finis. Cette phase a permis de tester la robustesse des méthodes et d’envisager une méthode de-embedding originale nommée Half-Thru Method. Cette méthode donne des résultats comparables à la méthode TRL, méthode qui reste la plus performante actuellement. Cependant il reste difficile d'expliquer l'origine des pertes supplémentaires obtenues notamment dans la mesure des lignes à ondes lentes S-CPW.Une troisième phase de modélisation a alors consisté à prendre en compte les pointes de mesure et les cellules adjacentes à notre dispositif sous test. Plus de 80 structures de test ont été conçues en technologie AMS 0,35μm afin de comparer les différentes méthodes de de-embedding et d’en analyser les couplages avec les structures adjacentes, les pointes de mesure et les modes de propagation perturbatifs.Finalement, ce travail a permis de dégager un certain nombre de précautions à considérer à l’attention des concepteurs de circuits microélectroniques désirant caractériser leur circuit avec précision au-delà de 110 GHz. Il a également permis de mettre en place la méthode de de-embedding Half-Thru Method qui n'est basée sur aucun modèle électrique, au contraire des autres méthodes

Antenna-coupled TES bolometers used in BICEP2, Keck array, and SPIDER

We have developed antenna-coupled transition-edge sensor (TES) bolometers for a wide range of cosmic microwave background (CMB) polarimetry experiments, including BICEP2, Keck Array, and the balloon borne SPIDER. These detectors have reached maturity and this paper reports on their design principles, overall performance, and key challenges associated with design and production. Our detector arrays repeatedly produce spectral bands with 20%-30% bandwidth at 95, 150, or 220~GHz. The integrated antenna arrays synthesize symmetric co-aligned beams with controlled side-lobe levels. Cross-polarized response on boresight is typically ~0.5%, consistent with cross-talk in our multiplexed readout system. End-to-end optical efficiencies in our cameras are routinely 35% or higher, with per detector sensitivities of NET~300 uKrts. Thanks to the scalability of this design, we have deployed 2560 detectors as 1280 matched pairs in Keck Array with a combined instantaneous sensitivity of ~9 uKrts, as measured directly from CMB maps in the 2013 season. Similar arrays have recently flown in the SPIDER instrument, and development of this technology is ongoing.Comment: 16 pgs, 20 fig

Reconfigurable Metasurfaces for Beam Scanning Planar Antennas

We are studying the implementation of 'Scanning Antenna dedicated to the applications of satellite communications geostationary. The structures developed are suitable for to be on board an airplane or a train. The architecture of the antenna developed consists of a double linear network in two transverse dimmensions. The scan in each network is provided by the lines coplanar to metamaterials controlled by varactor. We porposons of new methods characterization of discontinuities coplanar online for the line design. In addition, a energy harvesting system has be designed to feed radiating elements and tested with patch different antennas. Finally, we are considering co-integration radiating structures and CRLH lines as well as control electronic by the diodes

High frequency signal integrity in high-density assemblies

The demand for faster, portable and reliable electronic devices is increasing the pressure on the development of assembly techniques for signal integrity (SI). The advance of integrated circuits toward a large number of Input/Output (I/Os), a high number of operations and up to microwave communication frequencies, is behind the drive for the search for new packaging solutions. The materials and assembly techniques have an important impact on the propagation of high speed signals. Signal integrity issues emerge due to the electrical losses of materials, reflections from impedance discontinuities in the signal path and fast transitions of the signals. For these reasons, signal integrity in lead-free connections of WLCSP, flip chip (FC) and Integrated Module Board (IMB) assemblies were investigated up to 50 GHz. The increase of conductor loss resulting from the presence of thick oxide layers on the surface of solder bumps of hot running components was experimentally studied for the first time. Utilizing theoretical calculations, a design rule was developed to account for the 40 % increase in losses due to the presence of oxide layers at high frequencies. The research into the influence of solder microstructure on signal quality showed that it did not negatively affect the wave propagation. Experimental results proved that the presence of underfills and high density routing on printed wiring boards (PWBs) under the WLCSP components, detuned the components and the connections. The effects of three different underfills on signal propagation were studied. It was proven that the changes resulting from the rheology and parameters of curing process influence the losses and reflections of circuits. The analysis of microwave performances of flip chip (FC) and Integrated Module Board (IMB) assembly techniques demonstrated that they are well suited to Radio frequency (RF) and high speed applications. Comparison showed that IMB performed better as the wave encountered smaller discontinuities and had an optimized propagation path. Full wave simulations of IMB assemblies were performed considering finite ground coplanar waveguide (FGCPW), microstrip and stripline connections with stack-ups that included high dielectric constant materials and four connection possibilities. The research was carried out in the domains of both frequency and time to rigorously determine the sources of signal reflections. The results emphasized that in the design for match impedance and optimal current return path, discontinuities and reference planes had significant impact on signal integrity

Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)

A micromachined zipping variable capacitor

Micro-electro-mechanical systems (MEMS) have become ubiquitous in recent years and are found in a wide range of consumer products. At present, MEMS technology for radio-frequency (RF) applications is maturing steadily, and significant improvements have been demonstrated over solid-state components. A wide range of RF MEMS varactors have been fabricated in the last fifteen years. Despite demonstrating tuning ranges and quality factors that far surpass solid-state varactors, certain challenges remain. Firstly, it is difficult to scale up capacitance values while preserving a small device footprint. Secondly, many highly-tunable MEMS varactors include complex designs or process flows. In this dissertation, a new micromachined zipping variable capacitor suitable for application at 0.1 to 5 GHz is reported. The varactor features a tapered cantilever that zips incrementally onto a dielectric surface when actuated electrostatically by a pulldown electrode. Shaping the cantilever using a width function allows stable actuation and continuous capacitance tuning. Compared to existing MEMS varactors, this device has a simple design that can be implemented using a straightforward process flow. In addition, the zipping varactor is particularly suited for incorporating a highpermittivity dielectric, allowing the capacitance values and tuning range to be scaled up. This is important for portable consumer electronics where a small device footprint is attractive. Three different modelling approaches have been developed for zipping varactor design. A repeatable fabrication process has also been developed for varactors with a silicon dioxide dielectric. In proof-of-concept devices, the highest continuous tuning range is 400% (24 to 121 fF) and the measured quality factors are 123 and 69 (0.1 and 0.7 pF capacitance, respectively) at 2 GHz. The varactors have a compact design and fit within an area of 500 by 100 μm