95 research outputs found
SNDR Limits of Oscillator-Based Sensor Readout Circuits.
This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.This work has been funded by projects 610484 FP7-IAPP of the European Union and TEC2014-56879-R of CICYT, Spain. The authors would like to thank Roberto Nonis and Pedro Amaral from Infineon Technologies Austria AG for helpful discussions
Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones
Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits
and data converters based on frequency-encoding. This research
has been motivated by the needs of consumer electronics industry, which
constantly demands more compact readout circuit for MEMS microphones
and other sensors. Nowadays, data acquisition is mainly based
on encoding signals in voltage or current domains, which is becoming
more challenging in modern deep submicron CMOS technologies.
Frequency-encoding is an emerging signal processing technique based
on encoding signals in the frequency domain. The key advantage of
this approach is that systems can be implemented using mostly-digital
circuitry, which benefits from CMOS technology scaling. Frequencyencoding
can be used to build phase referenced integrators, which can
replace classical integrators (such as switched-capacitor based integrators)
in the implementation of efficient analog-to-digital converters and
sensor interfaces. The core of the phase referenced integrators studied in
this thesis consists of the combination of different oscillator topologies
with counters and highly-digital circuitry.
This work addresses two related problems: the development of capacitive
MEMS sensor readout circuits based on frequency-encoding, and the
design and implementation of compact oscillator-based data converters
for audio applications.
In the first problem, the target is the integration of the MEMS sensor
into an oscillator circuit, making the oscillation frequency dependent on
the sensor capacitance. This way, the sound can be digitized by measuring
the oscillation frequency, using digital circuitry. However, a MEMS
microphone is a complex structure on which several parasitic effects can
influence the operation of the oscillator. This work presents a feasibility
analysis of the integration of a MEMS microphone into different oscillator
topologies. The conclusion of this study is that the parasitics of the
MEMS limit the performance of the microphone, making it inefficient.
In contrast, replacing conventional ADCs with frequency-encoding based
ADCs has proven a very efficient solution, which motivates the next
problem.
In the second problem, the focus is on the development of high-order
oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical
integrators and phase referenced integrators has been studied, followed
by an overview of state-of-art oscillator-based converters. Then,
a procedure to replace classical integrators by phase referenced integrators
is presented, including a design example of a second-order oscillator based
Sigma-Delta modulator. Subsequently, the main circuit impairments that
limit the performance of this kind of implementations, such as phase
noise, jitter or metastability, are described.
This thesis also presents a methodology to evaluate the impact of
phase noise and distortion in oscillator-based systems. The proposed
method is based on periodic steady-state analysis, which allows the rapid
estimation of the system dynamic range without resorting to transient
simulations. In addition, a novel technique to analyze the impact of
clock jitter in Sigma-Delta modulators is described.
Two integrated circuits have been implemented in 0.13 μm CMOS
technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder
noise shaping using only oscillators and digital circuitry. The first
testchip shows a malfunction in the digital circuitry due to the complexity
of the multi-bit counters. The second chip, implemented using
single-bit counters for simplicity, shows second-order noise shaping and
reaches 103 dB-A of dynamic range in the audio bandwidth, occupying
only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces
para sensores capacitivos basados en codificación en frecuencia. Esta
investigación está motivada por las necesidades de la industria, que constantemente
demanda reducir el tamaño de este tipo de circuitos. Hoy en
día, la adquisición de datos está basada principalmente en la codificación
de señales en tensión o en corriente. Sin embargo, la implementación
de este tipo de soluciones en tecnologías CMOS nanométricas presenta
varias dificultades.
La codificación de frecuencia es una técnica emergente en el procesado
de señales basada en codificar señales en el dominio de la frecuencia.
La principal ventaja de esta alternativa es que los sistemas pueden implementarse
usando circuitos mayoritariamente digitales, los cuales se
benefician de los avances de la tecnología CMOS. La codificación en
frecuencia puede emplearse para construir integradores referidos a la
fase, que pueden reemplazar a los integradores clásicos (como los basados
en capacidades conmutadas) en la implementación de conversores
analógico-digital e interfaces de sensores. Los integradores referidos a la
fase estudiados en esta tesis consisten en la combinación de diferentes
topologías de osciladores con contadores y circuitos principalmente digitales.
Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos
de lectura para sensores MEMS capacitivos basados en codificación
temporal, y el diseño e implementación de conversores de datos
compactos para aplicaciones de audio basados en osciladores.
En el primer caso, el objetivo es la integración de un sensor MEMS
en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado
midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos
en su mayor parte digitales. Sin embargo, un micrófono MEMS es
una estructura compleja en la que múltiples efectos parasíticos pueden
alterar el correcto funcionamiento del oscilador. Este trabajo presenta
un análisis de la viabilidad de integrar un micrófono MEMS en diferentes
topologías de oscilador. La conclusión de este estudio es que los parasíticos
del MEMS limitan el rendimiento del micrófono, causando que esta
solución no sea eficiente. En cambio, la implementación de conversores
analógico-digitales basados en codificación en frecuencia ha demostrado
ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente
problema.
La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado
la equivalencia entre los integradores clásicos y los integradores
referidos a la fase, seguido de una descripción de los conversores basados
en osciladores publicados en los últimos años. A continuación se
presenta un procedimiento para reemplazar integradores clásicos por integradores
referidos a la fase, incluyendo un ejemplo de diseño de un
modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente
se describen los principales problemas que limitan el rendimiento de este
tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad.
Esta tesis también presenta un nuevo método para evaluar el impacto
del ruido de fase y de la distorsión en sistemas basados en osciladores. El
método propuesto está basado en simulaciones PSS, las cuales permiten
la rápida estimación del rango dinámico del sistema sin necesidad de
recurrir a simulaciones temporales. Además, este trabajo describe una
nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta.
En esta tesis se han implementado dos circuitos integrados en tecnología
CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los
moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han
sido diseñados para producir conformación espectral de ruido de segundo
orden, usando únicamente osciladores y circuitos mayoritariamente digitales.
El primer chip ha mostrado un error en el funcionamiento de los
circuitos digitales debido a la complejidad de las estructuras multi-bit
utilizadas. El segundo chip, implementado usando contadores de un solo
bit con el fin de simplificar el sistema, consigue conformación espectral
de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el
ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow
A VCO-based CMOS readout circuit for capacitive MEMS microphones
Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.This research was funded by project TEC2017-82653-R of CICYT, Spain
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS : part 1: basic principles
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs. The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling. Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues. Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance. This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation
In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight
VCO-based ADC with a simplified DAC for non-linearity correction
The performance of open-loop ADCs implemented with VCOs is limited by VCO non-linearity and first-order noise shaping. The resolution limitation imposed by first-order noise shaping can be compensated by a ring oscillator VCO with many output phases. Linearity can also be improved by using a feedback loop around the VCO closed with a DAC. However, a long ring oscillator may require a DAC with a prohibitive number of bits if feedback is used to compensate distortion. This Letter proposes an ADC architecture based on the Leslie-Singh Sigma-Delta (Σ∆) modulator that allows to implement a distortion correction loop around a VCO with a simplified DAC of few levels, yet keeping a large number of output quantisation levels to maintain resolution. The Letter discusses the system-level architecture and shows an implementation circuit example to verify the effective correction of distortion.This work has been supported by the CICYT project TEC2014-56879-R, Spain
Dopamiinin hapettumisen lukija-anturirajapinta 65 nm CMOS teknologialla
Sensing and monitoring of neural activities within the central nervous system has become a fast-growing area of research due to the need to understand more about how neurons communicate. Several neurological disorders such as Parkinson’s disease, Schizophrenia, Alzeihmers and Epilepsy have been reported to be associated with imbalance in the concentration of neurotransmitters such as glutamate and dopamine [1] - [5]. Hence, this thesis proposes a solution for the measurement of dopamine concentration in the brain during neural communication.
The proposed design of the dopamine oxidation readout sensor interface is based on a mixed-signal front-end architecture for minimizing noise and high resolution of detected current signals. The analog front-end is designed for acquisition and amplification of current signals resulting from oxidation and reduction at the biosensor electrodes in the brain. The digital signal processing (DSP) block is used for discretization of detected dopamine oxidation and reduction current signals that can be further processed by an external system.
The results from the simulation of the proposed design show that the readout circuit has a current resolution of 100 pA and can detect minimum dopamine concentration of 10 μMol based on measured data from novel diamond-like carbon electrodes [6]. Higher dopamine concentration can be detected from the sensor interface due to its support for a wide current range of 1.2 μA(±600 nA). The digital code representation of the detected dopamine has a resolution of 14.3-bits with RMS conversion error of 0.18 LSB which results in an SNR of 88 dB at full current range input. However, the attained ENOB is 8-bits due to the effect of nonlinearity in the oscillator based ADC. Nonetheless, the achieved resolution of the readout circuit provides good sensitivity of released dopamine in the brain which is useful for further understanding of neurotransmitters and fostering research into improved treatments of related neurodegenerative diseases.Keskushermoston aktiivisuuden havainnointi ja tarkkailu on muodostunut tärkeäksi tutkimusalaksi, sillä tarve ymmärtää neuronien viestintää on kasvanut. Monien hermostollisten sairauksien kuten Parkinsonin taudin, skitsofrenian, Alzheimerin taudin ja epilepsian on huomattu aiheuttavan muutoksia välittäjäaineiden, kuten glutamaatin ja dopamiinin, pitoisuuksissa [1] - [5]. Aiheeseen liittyen tässä työssä esitetään ratkaisu dopamiinipitoisuuden mittaamiseksi aivoista.
Esitetty dopamiinipitoisuuden lukijapiiri perustuu sekamuotoiseen etupäärakenteeseen, jolla saavutetaan matala kohinataso ja hyvä tarkkuus signaalien ilmaisemisessa. Suunniteltu analoginen etupää kykenee lukemaan ja vahvistamaan dopamiinipitoisuuden muutosten aiheuttamia virran muutoksia aivoihin asennetuista elektrodeista. Digitaalisen signaalinkäsittelyn avulla voidaan havaita dopamiinin hapettumis-ja pelkistymisvirtasignaalit, ja välittää ne edelleen ulkoisen järjestelmän muokattavaksi.
Simulaatiotulokset osoittavat, että suunniteltu piiri saavuttaa 100 pA virran erottelukyvyn. Simuloinnin perustuessa hiilipohjaisiin dopamiinielektrodeihin piiri voi havaita 10 μMol dopamiinipitoisuuden [6]. Myös suurempia dopamiinipitoisuuksia voidaan havaita, sillä etupäärajapinta tukee 1.2 μA(±600 nA) virta-aluetta. Digitaalinen esitysmuoto tukee 14.3 bitin esitystarkkuutta 0.18 bitin RMS virheellä saavuttaen 88 dB dynaamisen virta-alueen. Saavutettu ENOB (tehollinen bittimäärä) on kuitenkin 8 bittiä oskillaattoripohjaisen ADC:n (analogia-digitaalimuuntimen) epälineaarisuuden takia. Saavutettu tarkkuus tuottaa hyvän herkkyyden dopamiinin havaitsemiseksi ja hyödyttää siten välittäjäainetutkimusta ja uusien hoitomuotojen kehittämistä hermostollisiin sairauksiin
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