ROUTING WITH MINIMUM WIRE LENGTH IN THE MANHATTAN MODEL IS NP-COMPLETE

The present paper concentrates on one of the most common routing models, on the Manhattan model where horizontal and vertical wire segments are positioned on different sides of the board. While the minimum width can be found in linear time in the single row routing, apparently there was no efficient algorithm to find the minimum wire length. We showed before that this problem is NP-complete in the dogleg-free case but the complexity of the problem was still unknown in the general case. In this paper we modify the construction applied in the former proof in order to show the NP-completeness of routing with minimum wire length in the Manhattan model without any restrictions

OPTIMAL ROUTING ON NARROW CHANNELS

Channel routing is one of the basic problems in VLSI routing. While the minimum width can be found in linear time in the single row routing problem, the complexity of the channel routing problem is not fully understood yet. A solution can be found, even in linear time, in the unconstrained model, but the complexity of determining the minimum width is not known. The present article concentrates on the Manhattan model where horizontal and vertical wire segments are positioned on different sides of the board. In this case, the routing problem is known to be NP-complete. Hence there is no hope to find an algorithm whose running time is polynomial both in the length and the width of the channel. The width of the channel is usually much smaller than the length, thus, an algorithm, whose running time is exponential in the width and polynomial' in the length can be efficient in the case of a narrow channel. We show that the channel routing problem in the Manhattan model is solvable in linear time if the length of the input is proportional to the length of the channel, and the width does not belong to the input

Intra Region Routing

The custom integrated circuit routing problem normally requires partitioning into rectangular routing regions. Natural partitions usually result in regions that form both channels and areas . This dissertation introduces several new channel and area routing algorithms and measures their performance. A formal description of the channel routing problem is presented and a relationship is established between the selection of intervals for each track and the number of tracks in the completed channel. This relationship is used as an analysis tool that leads to the development of two new and highly effective channel routing algorithms: the Revised and LCP algorithms. The performance of these algorithms is compared against the Dogleg, Greedy, and several area routing algorithms over sets of randomly generated channels. The results indicate performance increases ranging from 2.74 to 34 times, depending on the characteristics of the channel. In area routing, a new Degree of Freedom (DOF) based algorithm is developed that is straightforward to implement, is extensible to multipoint nets and reports if a path does not exist to complete the net. The quality of area routing algorithms is measured by the difficulty of the areas that can be successfully routed over sets of randomly generated areas. An extended definition of Manhattan Area Measure (MAM) is introduced as a measure of the difficulty of completing the wiring for areas with multipoint nets. The results show that the DOF algorithm has higher completion rates than the Lee algorithm. This difference is greatest in areas with high aspect ratios. A new measure of the difficulty of an area is developed that places upper bounds on the performance of area routing algorithms. In areas with low aspect ratios, the drop in algorithm completion rates is closely related to this upper bound

An automated routing method for VLSI with three interconnection layers

Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. In this thesis, we examine the VLSI routing problem where three layers are available for interconnection;We investigate the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for three-interconnection layer model is not much different from that of two-layer madel. We study the global routing problem for two cases: gate array and general cell layout. In our three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on;The channel routing stage of our router is based on directional model where overlaps of horizontal wire segments are allowed. We improve the dogleg method so that it is applicable to the three-layer model and it can handle multi-terminal nets more efficiently. Applying the extensive dogleg method and the three-layer merge algorithm, we not only remove the cyclic vertical constraints graph but also eliminate the effect of the height of long vertical constraints tree to the channel width and thus we reduce the lower bound of the channel width to half of the density of the channel. We expand the applicability of channel router by eliminating some of the limitations assumed in channel routing problems by some existing algorithms. Routability conditions are examined for various cases of channel routing problem;The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing which minimizes the channel width and the wire length. Experimental results show that our router is close to optimal

A Density-Based General Greedy Channel Routing Algorithm in VLSI Design Automation.

One of the most important forms of routing strategies is called channel routing . This approach allows us to reduce the extremely difficult VLSI layout problem to a collection of simpler subproblems. For channel routing problems, most frequently mentioned heuristic algorithms use parameters derived from experiments to approach the routing solution without carefully considering the effect of each selected wire segment to the final routing solution. In this dissertation, we propose a new channel routing algorithm in the two-layer restricted-Manhattan routing model (2-RM) in detail. There are three phases involved in developing the new routing algorithm. In the first phase, we distinguish one type of wire from the others using some optimality criteria, which makes the selection of a set of best horizontal wire segments for a track more effective so that good performance of the generated routing solutions can be achieved. In the second phase, we develop a theoretical framework related to two major data structures, column density and vertical constraint graph, which effectively improves search efficiency and routing performance. Finally in the third phase, we develop an efficient powerful heuristic channel routing algorithm based on the concepts shown in phase one and the theoretical framework proposed in phase two. We highlight the application of our algorithm to the channel routing problems in the three-layer restricted-Manhattan overlap (3-RM-O) and three-layer Manhattan overlay (3-M-O) routing models. On many tests we have conducted on the examples known in the literature, our algorithm has performed as well or better than the existing algorithms in both 2-RM and 3-M-O routing models. Our experiments show that our approach has the potential to outperform other algorithms in other routing models

MulCh: a Multi-layer Channel Router using One, Two, and Three Layer Partitions

Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels with any number of layers and automatically chooses a good assignment of wiring strategies to the different layers. In test cases, MulCh shows significant improvement over Chameleon in terms of channel width, net length, and number of vias

Channel routing: Efficient solutions using neural networks

Neural network architectures are effectively applied to solve the channel routing problem. Algorithms for both two-layer and multilayer channel-width minimization, and constrained via minimization are proposed and implemented. Experimental results show that the proposed channel-width minimization algorithms are much superior in all respects compared to existing algorithms. The optimal two-layer solutions to most of the benchmark problems, not previously obtained, are obtained for the first time, including an optimal solution to the famous Deutch\u27s difficult problem. The optimal solution in four-layers for one of the be lchmark problems, not previously obtained, is obtained for the first time. Both convergence rate and the speed with which the simulations are executed are outstanding. A neural network solution to the constrained via minimization problem is also presented. In addition, a fast and simple linear-time algorithm is presented, possibly for the first time, for coloring of vertices of an interval graph, provided the line intervals are given

Minimum Sum Edge Colorings of Multicycles

In the minimum sum edge coloring problem, we aim to assign natural numbers to edges of a graph, so that adjacent edges receive different numbers, and the sum of the numbers assigned to the edges is minimum. The {\em chromatic edge strength} of a graph is the minimum number of colors required in a minimum sum edge coloring of this graph. We study the case of multicycles, defined as cycles with parallel edges, and give a closed-form expression for the chromatic edge strength of a multicycle, thereby extending a theorem due to Berge. It is shown that the minimum sum can be achieved with a number of colors equal to the chromatic index. We also propose simple algorithms for finding a minimum sum edge coloring of a multicycle. Finally, these results are generalized to a large family of minimum cost coloring problems

Efficient Interconnection Schemes for VLSI and Parallel Computation

This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson\u27s fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these universal networks can efficiently simulate competing networks by means of an appropriate correspondence between network components and efficient algorithms for routing messages on the universal network. In particular, a universal network of area A can simulate competing networks with O(lg^3A) slowdown (in bit-times), using a very simple randomized routing algorithm and simple network components. Alternatively, a packet routing scheme of Leighton, Maggs, and Rao can be used in conjunction with more sophisticated switching components to achieve O(lg^2 A) slowdown. Several other important aspects of universality are also discussed. It is shown that universal networks can be constructed in area linear in the number of processors, so that there is no need to restrict the density of processors in competing networks. Also results are presented for comparisons between networks of different size or with processors of different sizes (as determined by the amount of attached memory). Of particular interest is the fact that a universal network built from sufficiently small processors can simulate (with the slowdown already quoted) any competing network of comparable size regardless of the size of processors in the competing network. In addition, many of the results given do not require the usual assumption of unit wire delay. Finally, though most of the discussion is in the two-dimensional world, the results are shown to apply in three dimensions by way of a simple demonstration of general results on graph layout in three dimensions. The second main problem considered in this thesis is channel routing when many layers of interconnect are available, a scenario that is becoming more and more meaningful as chip fabrication technologies advance. This thesis describes a system MulCh for multilayer channel routing which extends the Chameleon system developed at U. C. Berkeley. Like Chameleon, MulCh divides a multilayer problem into essentially independent subproblems of at most three layers, but unlike Chameleon, MulCh considers the possibility of using partitions comprised of a single layer instead of only partitions of two or three layers. Experimental results show that MulCh often performs better than Chameleon in terms of channel width, total net length, and number of vias. In addition to a description of MulCh as implemented, this thesis provides improved algorithms for subtasks performed by MulCh, thereby indicating potential improvements in the speed and performance of multilayer channel routing. In particular, a linear time algorithm is given for determining the minimum width required for a single-layer channel routing problem, and an algorithm is given for maintaining the density of a collection of nets in logarithmic time per net insertion. The last part of this thesis shows that straightforward techniques for implementing finite-state machines are optimal in the worst case. Specifically, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires (ks lg s) area to lay out its realization. For nondeterministic machines, there is an analogous lower bound of (ks^2) area

A one-to-one correspondence between potential solutions of the cluster deletion problem and the minimum sum coloring problem, and its application to P 4 -sparse graphs

In this note we show a one-to-one correspondence between potentially optimal solutions to the cluster deletion problem in a graph G and potentially optimal solutions for the minimum sum coloring problem in G (i.e. the complement graph of G). We apply this correspondence to polynomially solve the cluster deletion problem in a subclass of P 4 -sparse graphs that strictly includes P 4 -reducible graphs